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Product details

Parameters

Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 583 Architecture Pipeline SNR (dB) 75 ENOB (Bits) 11.7 SFDR (dB) 77 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RHA) 40 36 mm² 6 x 6 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate: 3.125 Gbps
    • Meets JEDEC JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA to 32 mA
  • Power Dissipation:
    • 583 mW at 160 MSPS in Dual-Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • SNR at 185-MHz IF: –72.7 dBFS
  • Analog Input Dynamic Range: 2 VPP
  • Reference Support:
    External and Internal (Trimmed)
  • Supply:
    • Analog and Digital: 1.8 V
    • Input Buffer: 3.3 V
  • Programmable Digital Gain: 0 dB to 6 dB
  • Output: Straight Offset Binary or
    Twos Complement
  • Package: 6-mm × 6-mm QFN-40
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Description

The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.

The device is specified over the industrial temperature range (–40°C to +85°C).

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Technical documentation

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Type Title Date
* Data sheet 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Outp datasheet (Rev. B) Oct. 04, 2013
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
User guide ADS61JBxx EVM User's Guide (Rev. A) Sep. 30, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
GUI FOR EVALUATION MODULE (EVM) Download
SLAC530.ZIP (82937 KB)

Design tools & simulation

SIMULATION MODEL Download
SLOM341.ZIP (110 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RHA) 40 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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