CSI RX writes CSI-2 received pixel data into DDR. Once a frame is written, host is triggered to initiate VISS processing. HTS will go through 'init' sequence to initialize VISS and its SL2 pointers. As UDMA is head of pipeline for memory to memory mode of image processing, its scheduler inside HTS needs to be configured for generating "frame height" number of triggers to fetch image lines one by one. This is essential to bring determinism in pipeline as there is no producer for UDMA load thread.
The following memory to memory operation steps are illustrated in Figure 7-26:
- CSi-2 stream captured via CSI RX into DDR. This traffic must be routed through Real Time fabric of NAVSS/MSMC. CSI RX capture happens independent of VISS processing.
- Init from HTS to initialize VISS.
- HTS triggers UDMA to fetch data for processing. There could be max 3 independent input data.
- UDMA loads the data and stores into SL2.
- Upon completion of all input buffer loading (at line level) UDMA channel 'done' event triggers VISS thread start (still needs to ensure there are buffer available for writing VISS output data).
- VISS produces line #N corresponding to loading of
line #N + vertical_latency.
- 'Tdone' triggered to HTS.
- HTS triggers UDMA for output buffer transfer into DDR.
- UDMA loads data from SL2 and write into DDR.
The following asumptions are made for the memory to memory operation described above:
- CSI RX write is mapped onto hard real time fabric of NavSS/MSMC.
- Configurable vertical blanking times 'Tstart'
generated by HTS to let RFE + NSF4V + GLBCE + FCP flush its internal pipe, eventhough
last line of current frame is already fed into RFE.
- Buffer dependencies:
- RFE input buffer (exp0, exp1, exp2)
- H3A output Buffer (AE or AF)
- FCP output Buffer (Y12, UV12, Y8, UV8, S8)