MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
MCSPI0 |
MCSPI0_intr_spi_0 |
GICSS0_spi_IN_204 |
GICSS0 |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
R5FSS0_CORE0_intr_IN_204 |
R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_204 |
WKUP_R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_204 |
MCU_R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_204 |
C7X256V0_CLEC |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_204 |
C7X256V1_CLEC |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
TIFS0_nvic_IN_84 |
TIFS0 |
MCSPI0 interrupt request |
level |
MCSPI0 |
MCSPI0_intr_spi_0 |
HSM0_nvic_IN_84 |
HSM0 |
MCSPI0 interrupt request |
level |
MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
MCSPI1 |
MCSPI1_intr_spi_0 |
GICSS0_spi_IN_205 |
GICSS0 |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
R5FSS0_CORE0_intr_IN_205 |
R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_205 |
WKUP_R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_205 |
MCU_R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_205 |
C7X256V0_CLEC |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_205 |
C7X256V1_CLEC |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
TIFS0_nvic_IN_87 |
TIFS0 |
MCSPI1 interrupt request |
level |
MCSPI1 |
MCSPI1_intr_spi_0 |
HSM0_nvic_IN_87 |
HSM0 |
MCSPI1 interrupt request |
level |
MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
MCSPI2 |
MCSPI2_intr_spi_0 |
GICSS0_spi_IN_206 |
GICSS0 |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
R5FSS0_CORE0_intr_IN_206 |
R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_206 |
WKUP_R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_206 |
MCU_R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_206 |
C7X256V0_CLEC |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_206 |
C7X256V1_CLEC |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
TIFS0_nvic_IN_88 |
TIFS0 |
MCSPI2 interrupt request |
level |
MCSPI2 |
MCSPI2_intr_spi_0 |
HSM0_nvic_IN_88 |
HSM0 |
MCSPI2 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
GICSS0_spi_IN_208 |
GICSS0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
R5FSS0_CORE0_intr_IN_207 |
R5FSS0_CORE0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_207 |
WKUP_R5FSS0_CORE0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_207 |
MCU_R5FSS0_CORE0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_208 |
C7X256V0_CLEC |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_208 |
C7X256V1_CLEC |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
TIFS0_nvic_IN_85 |
TIFS0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI0 |
MCU_MCSPI0_intr_spi_0 |
HSM0_nvic_IN_85 |
HSM0 |
MCU_MCSPI0 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
GICSS0_spi_IN_209 |
GICSS0 |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
R5FSS0_CORE0_intr_IN_208 |
R5FSS0_CORE0 |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_208 |
WKUP_R5FSS0_CORE0 |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_208 |
MCU_R5FSS0_CORE0 |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_209 |
C7X256V0_CLEC |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_209 |
C7X256V1_CLEC |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
TIFS0_nvic_IN_86 |
TIFS0 |
MCU_MCSPI1 interrupt request |
level |
MCU_MCSPI1 |
MCU_MCSPI1_intr_spi_0 |
HSM0_nvic_IN_86 |
HSM0 |
MCU_MCSPI1 interrupt request |
level |