SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The goal of the basic high-level programming model is to introduce a top-down approach to users that need to configure the GPMC module.
Figure 12-158 and Table 12-164 through Table 12-165 show a programming model top-level diagram for the GPMC, and a description of each step. Each block of the diagram is described in one of the following sections through a set of registers to configure.
Step | Description |
---|---|
NOR Memory Type | See Table 12-166. |
NOR Chip-Select Configuration | See Table 12-167. |
NOR Timings Configuration | See Table 12-168. |
WAIT Pin Configuration | See Table 12-176. |
Enable Chip-Select | See Table 12-177. |
Step | Description |
---|---|
NAND Memory Type | See Table 12-171. |
NAND Chip-Select Configuration | See Table 12-172. |
Write Operations (Asynchronous) | See Table 12-173. |
Read Operations (Asynchronous) | See Table 12-173. |
ECC Engine | See Table 12-174. |
Prefetch and Write-Posting Engine | See Table 12-175. |
WAIT Pin Configuration | See Table 12-176. |
Enable Chip-Select | See Table 12-177. |