SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VBUSM2AXI bridge implements a mechanism to drain the DDR controller. The drain action will temporarily pause the submission of commands to the controller until the read command(s) that triggered the drain operation have been resolved.
Each read going to the DDR controller will have an associated internal counter that starts at zero. This counter will increment for each write or read command given to the controller after that particular read is sent. If any read command counter exceeds the programmed threshold the bridge will start a drain action. The threshold can be programmed in EMIF_SSCFG_V2A_DRAIN_THRESH_REG.