SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each DMA buffer can be associated to the pipeline or merged with other DMA buffers. The total number of DMA buffers for each individual pipeline is from 0 (pipeline inactive) to number of pipelines (in that case all the DMA buffers are associated to a single pipeline) supported by the DMA engine.
The user is responsible for configuring correctly the number of DMA buffers to guarantee no underflow. The DMA buffers allocated to each pipeline shall be greater or equal to the minimum required DMA buffer to support the throughput and the system latency.
When the size of the buffer is changed, the thresholds shall be re-programmed by the user to reflect the new DMA buffer configuration. Increasing the size of the buffer used enables to put the interconnect and the system memory in standby for a longer period, therefore, leading to a possible system power reduction.
The low power mode of the DISPC DMA can also be achieved by keeping the thresholds (bit-fields [31-16] BUFHIGHTHRESHOLD and [15-0] BUFLOWTHRESHOLD of DSS0_VID_BUF_THRESHOLD register) farther apart. The farther they are there will be longer periods of idling on the DMA fetch interface resulting in lower power. The user needs to ensure a minimum value of BUFLOWTHRESHOLD, so that there is no underflow.