SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
A total of 3 destination channels are provided within the DMA for concurrent transfers from Tx per channel buffers to the various attached peripherals. Each Tx channel requires a single PSI-L thread. The Tx channels are allocated as follows:
Tx DMA Channel | Function | Channel Type | Trigger Mode | Data FIFO Address | Strobe MMR Address | Control FIFO Address |
---|---|---|---|---|---|---|
8000 | McASP 0 Tx Ch 0 | XY | edge | 000002B08000 | 000000000000 | 000000000000 |
8001 | McASP 1 Tx Ch 0 | XY | edge | 000002B18000 | 000000000000 | 000000000000 |
8002 | McASP 2 Tx Ch 0 | XY | edge | 000002B28000 | 000000000000 | 000000000000 |