SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VBUSM2AXI supports two VBUSM interfaces:
HPT will have priority over LPT. In addition to the thread priority, the bridge will also reorder commands within a particular thread based on VBUSM priority. Therefore, the execution of commands from the command FIFO can be out-of-order. As a result, the read data can also be returned out-of-order.
The bridge will NOT maintain data coherency across threads. However, coherency within a particular thread will be maintained.
For low area implementation, the same FIFO resources are shared between HPT and LPT for write status and read data return interfaces. Therefore, system must ensure that there is no pushback on the write status and read data return interfaces by LPT to guarantee execution of HPT is not blocked.