SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The LVDS display interface is provided via two single-link OLDITX modules, which receives parallel RGB pixel data and synchronization signals from DSS DISPC Video Port 1 (VP1). The VP1 pixel data format and timings are the same as described for VP2 in Section 12.9.1.2.1.1 and Section 12.9.1.2.1.2, respectively. OLDITX works only with 18-bit or 24-bit RGB input source data.
The OLDITX translates 21-bit or 28-bit wide video and sync data into 3-bit or 4-bit wide serial data, 7-bits deep. The 24-bit serialized RGB pixel data is transmitted on four LVDS data lanes, clocked by one clock lane. OLDITX can also be configured to transmit only 18-bit RGB data (6-bits/pixel color component) on three LVDS lanes, when connected to a low-resolution display panel. In 18-bit configuration, only three LVDS data lanes and one clock lane are active. The fourth data lane is disabled.
Table 12-418 describes the OLDITX output LVDS signals.
Module Pin | Device Level Signal | Type(1) | Description | Module Pin Reset Value |
---|---|---|---|---|
OLDI_DATA0X | OLDI_A0P | O | OLDI differential data lane A0 (+) | - |
OLDI_DATA0Y | OLDI_A0N | O | OLDI differential data lane A0 (-) | - |
OLDI_DATA1X | OLDI_A1P | O | OLDI differential data lane A1 (+) | - |
OLDI_DATA1Y | OLDI_A1N | O | OLDI differential data lane A1 (-) | - |
OLDI_DATA2X | OLDI_A2P | O | OLDI differential data lane A2 (+) | - |
OLDI_DATA2Y | OLDI_A2N | O | OLDI differential data lane A2 (-) | - |
OLDI_DATA3X | OLDI_A3P | O | OLDI differential data lane A3 (+) | - |
OLDI_DATA3Y | OLDI_A3N | O | OLDI differential data lane A3 (-) | - |
OLDI_CLOCKX | OLDI_CLKP | O | OLDI differential clock lane CLK (+) | - |
OLDI_CLOCKY | OLDI_CLKN | O | OLDI differential clock lane CLK (-) | - |
Table 12-419 shows the supported LVDS pixel components mapping for 18-bit and 24-bit output data modes. The OLDI mapping type is defined in DSS0_DSS_OLDI_CFG[3-1] MAP register field as follows:
Mode | Single-link | Single-link | Single-link | Dual-link | Dual-link | Dual-link |
---|---|---|---|---|---|---|
18-bit | 24-bit JEIDA | 24-bit | 18-bit | 24-bit JEIDA | 24-bit | |
OLDI mapping type | A | B | C | D | E | F |
Pixels per LVDS clock cycle | 1pixel/1clock | 1pixel/1clock | 1pixel/1clock | 2pixel/1clock | 2pixel/1clock | 2pixel/1clock |
Number of clock pairs | 1 | 1 | 1 | 1or2 | 1or2 | 1or2 |
Number of LVDS data pairs | 3 | 4 | 4 | 6 | 8 | 8 |
Color depth | 6 | 8 | 8 | 6 | 8 | 8 |
A00 | R0 | R2 | R0 | OR0 | OR2 | OR0 |
A01 | R1 | R3 | R1 | OR1 | OR3 | OR1 |
A02 | R2 | R4 | R2 | OR2 | OR4 | OR2 |
A03 | R3 | R5 | R3 | OR3 | OR5 | OR3 |
A04 | R4 | R6 | R4 | OR4 | OR6 | OR4 |
A05 | R5 | R7 | R5 | OR5 | OR7 | OR5 |
A06 | G0 | G2 | G0 | OG0 | OG2 | OG0 |
A10 | G1 | G3 | G1 | OG1 | OG3 | OG1 |
A11 | G2 | G4 | G2 | OG2 | OG4 | OG2 |
A12 | G3 | G5 | G3 | OG3 | OG5 | OG3 |
A13 | G4 | G6 | G4 | OG4 | OG6 | OG4 |
A14 | G5 | G7 | G5 | OG5 | OG7 | OG5 |
A15 | B0 | B2 | B0 | OB0 | OB2 | OB0 |
A16 | B1 | B3 | B1 | OB1 | OB3 | OB1 |
A20 | B2 | B4 | B2 | OB2 | OB4 | OB2 |
A21 | B3 | B5 | B3 | OB3 | OB5 | OB3 |
A22 | B4 | B6 | B4 | OB4 | OB6 | OB4 |
A23 | B5 | B7 | B5 | OB5 | OB7 | OB5 |
A24 | HSYNC | HSYNC | HSYNC | HSYNC | HSYNC | HSYNC |
A25 | VSYNC | VSYNC | VSYNC | VSYNC | VSYNC | VSYNC |
A26 | DEN | DEN | DEN | DEN | DEN | DEN |
A30 | See (1) | R0 | R6 | See (1) | OR0 | OR6 |
A31 | --- | R1 | R7 | --- | OR1 | OR7 |
A32 | --- | G0 | G6 | --- | OG0 | OG6 |
A33 | --- | G1 | G7 | --- | OG1 | OG7 |
A34 | --- | B0 | B6 | --- | OB0 | OB6 |
A35 | --- | B1 | B7 | --- | OB1 | OB7 |
A36 | --- | NA | NA | --- | NA | NA |
A40 | See (2) | See (2) | See (2) | ER0 | ER2 | ER0 |
A41 | --- | --- | --- | ER1 | ER3 | ER1 |
A42 | --- | --- | --- | ER2 | ER4 | ER2 |
A43 | --- | --- | --- | ER3 | ER5 | ER3 |
A44 | --- | --- | --- | ER4 | ER6 | ER4 |
A45 | --- | --- | --- | ER5 | ER7 | ER5 |
A46 | --- | --- | --- | EG0 | EG2 | EG0 |
A50 | --- | --- | --- | EG1 | EG3 | EG1 |
A51 | --- | --- | --- | EG2 | EG4 | EG2 |
A52 | --- | --- | --- | EG3 | EG5 | EG3 |
A53 | --- | --- | --- | EG4 | EG6 | EG4 |
A54 | --- | --- | --- | EG5 | EG7 | EG5 |
A55 | --- | --- | --- | EB0 | EB2 | EB0 |
A56 | --- | --- | --- | EB1 | EB3 | EB1 |
A60 | --- | --- | --- | EB2 | EB4 | EB2 |
A61 | --- | --- | --- | EB3 | EB5 | EB3 |
A62 | --- | --- | --- | EB4 | EB6 | EB4 |
A63 | --- | --- | --- | EB5 | EB7 | EB5 |
A64 | --- | --- | --- | NA | NA | NA |
A65 | --- | --- | --- | NA | NA | NA |
A66 | --- | --- | --- | DEN | DEN | DEN |
A70 | See (1) | --- | --- | See (1) | ER0 | ER6 |
A71 | --- | --- | --- | --- | ER1 | ER7 |
A72 | --- | --- | --- | --- | EG0 | EG6 |
A73 | --- | --- | --- | --- | EG1 | EG7 |
A74 | --- | --- | --- | --- | EB0 | EB6 |
A75 | --- | --- | --- | --- | EB1 | EB7 |
A76 | --- | --- | --- | --- | NA | NA |
Figure 12-461 and Figure 12-462 show the LVDS data output bit format (that is, the pixel bit numbers onto LVDS interface bit numbers). The rising edge of the LVDS clock occurs two LVDS sub-symbols before the current cycle of data. The clock is composed of a 4 LVDS sub-symbol high time and a 3 LVDS sub-symbol low time.
Figure 12-463 and Figure 12-464 show the OLDITX input data mapped to LVDS output and the serial bit positions.
The OLDITX LVDS signal lines support a minimum bit time of 0.866 ns. This corresponds to a maximum pixel clock rate of 165 MHz (for a single link operation). A bit time period (known as TUI or Time Unit Interval) consists of several timing parameters:
For more information on the OLDITX LVDS timing parameters, refer to device-specific Datasheet.