The CSI_RX_IF module supports the following features:
- Compliant to MIPI CSI v1.3
- Supports up to 16 virtual channels per input
(partial MIPI CSI v2.0 feature)
- Data rate up to 2.5 Gbps per lane (wire rate)
- Supports 1, 2, 3, or 4 Data Lane connection to DPHY_RX
- Programmable formats including YUV420, YUV422, RGB, Raw, and User Defined (over 25 different formats supported)
- One independent (simultaneous)
output stream:
- One (up to 32 Channels) DMA interface through a
128-bit PSI_L connection to DMSS for transfers to memory:
- Byte packed (32x4) format, elastic buffer
mode
- Max rate 1 data cycle every 4 main clocks
- ByteValid per byte in Last Data Phase (LDP)
- 32 thread ID’s supported (virtual channel &
data type combinations); Flexible number of
threads (32 Max)
- Virtual channels and data types mapped via mmr to
PSI_L thread ID’s
- Internal FF based FIFO; RAM based buffer
(2kx128)
- Functional and data path error interrupts
- ECC support