SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Figure 12-27 shows all of the MCSPI interface signals in peripheral mode.
Table 12-16 describes the MCSPI I/O signals in peripheral mode.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(1) |
---|---|---|---|---|
MCU_MCSPI[1-0] | ||||
SPICLK | MCU_SPI[1-0]_CLK | I | MCSPI serial clock input for peripheral mode. | HiZ |
SPIDAT[0] | MCU_SPI[1-0]_D0 | I(2) | MCSPI Data I/O for peripheral mode. | HiZ |
SPIDAT[1] | MCU_SPI[1-0]_D1 | O(3) | MCSPI Data I/O for peripheral mode. | HiZ |
SPIEN_[n] | MCU_SPI[1-0]_CSi | I(4) | MCSPI chip-select i input for peripheral mode. | HiZ |
MCSPI[4-0] | ||||
SPICLK | SPI[4-0]_CLK | I | MCSPI serial clock input for peripheral mode. | HiZ |
SPIDAT[0] | SPI[4-0]_D0 | I(2) | MCSPI Data I/O for peripheral mode. | HiZ |
SPIDAT[1] | SPI[4-0]_D1 | O(3) | MCSPI Data I/O for peripheral mode. | HiZ |
SPIEN_[n] | SPI[4-0]_CSi | I(4) | MCSPI chip-select i input for peripheral mode. | HiZ |
For SPI[4-0]_CLK and MCU_SPI[1-0]_CLK signals to work properly, the RXACTIVE bit of the appropriate CTRLMMR_MCU_PADCONFIGx/ CTRLMMR_PADCONFIGy registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.