The single stream operation will provide the smallest multi-lane IP configuration with the reduced registers configuration removing some control and status registers. The stream will not require a large FIFO configuration and the clock rates will be matched to simplify the implementation to single pixel transfers using all the available interface bits, (i.e. up to 32).
For single pixel stream configuration, elastic buffer, RAW8 Data type on VC2, one pixel per cycle:
- Configure the number of DPHY_RX lanes:
- See CSIRX_STATIC_CFG register
- Set Error Interrupt mask:
- See CSIRX_ERROR_IRQS_MASK_CFG register
- Set the Pixel Interface and FIFO configuration. See CSIRX_STREAM0_CFG -
CSIRX_STREAM3_CFG.
- Set [9-8] FIFO_MODE to select the elastic buffer
configuration -> ‘1’
- Set the FIFO fill level that will determines the
FIFO depth that must be reached before data is output ->
0x0000
- Select the number of pixels to be output on each
cycle -> ‘0’.
- Set the type of
stream interface to “pixel” mode -> ‘0’
- Select the virtual channel and data types to be processed. See
CSIRX_STREAM0_DATA_CFG - CSIRX_STREAM3_DATA_CFG register.
- Set [31-16] VC_SELECT and virtual channel bits if
not supporting all virtual channels -> 1h, 2h
- Set [7] ENABLE_DT0 and [5-0] DATATYPE_SELECT0
values for one or both data types (default all DT) -> 0h, 1h,
2Ah
- Enable the stream to begin processing the incoming data from the DPHY_RX. See
CSIRX_STREAM0_CTRL - CSIRX_STREAM3_CTRL.
- Set [0] START bit -> ‘1’
The stream will begin to pass pixel data matching the configuration on the next frame start.