SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Please refer to Section 5.4.1 for more information that applies to SPI boot mode
The SPI boot mode supports the 1S-1S-1S mode only. The Read Command is 8-bits (0x03) followed by a 24 bit (3 byte) address. There are no dummy cycles issued after the read command. The frequency of operation supported is 6.250 MHz. OSPI0_D0 will have data transfers FROM the processor TO the flash device, and OSPI0_D1 will have data transfers TO the processor FROM the flash device