SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
---|---|---|---|---|---|---|---|
MCASP0 | PSC0 | GP_CORE | LPSC_MAIN_MCASP0 | 17 | OFF | YES | LPSC_MAIN_IP |
MCASP1 | PSC0 | GP_CORE | LPSC_MAIN_MCASP1 | 18 | OFF | YES | LPSC_MAIN_IP |
MCASP2 | PSC0 | GP_CORE | LPSC_MAIN_MCASP2 | 19 | OFF | YES | LPSC_MAIN_IP |
MCASP3 | PSC0 | GP_CORE | LPSC_MAIN_GPCORE_RSVD3 | 50 | OFF | YES | LPSC_MAIN_IP |
MCASP4 | PSC0 | GP_CORE | LPSC_MAIN_GPCORE_RSVD3 | 50 | OFF | YES | LPSC_MAIN_IP |
Module Instance | Source | Description |
---|---|---|
MCASP0 | PSC0 | MCASP0 reset |
MCASP1 | PSC0 | MCASP1 reset |
MCASP2 | PSC0 | MCASP2 reset |
MCASP3 | 0 | NONE |
MCASP4 | 0 | NONE |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
MCASP0 | MCASP0_rec_dma_event_req_0 | PDMA2_mcasp_main_0_rx_IN_0 | PDMA2 | MCASP0 interrupt request | pulse |
MCASP0 | MCASP0_rec_intr_pend_0 | GICSS0_spi_IN_267 | GICSS0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | R5FSS0_CORE0_intr_IN_120 | R5FSS0_CORE0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_120 | MCU_R5FSS0_CORE0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_267 | C7X256V0_CLEC | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_267 | C7X256V1_CLEC | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | TIFS0_nvic_IN_116 | TIFS0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_rec_intr_pend_0 | HSM0_nvic_IN_116 | HSM0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_dma_event_req_0 | PDMA2_mcasp_main_0_tx_IN_0 | PDMA2 | MCASP0 interrupt request | pulse |
MCASP0 | MCASP0_xmit_intr_pend_0 | GICSS0_spi_IN_268 | GICSS0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | R5FSS0_CORE0_intr_IN_121 | R5FSS0_CORE0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_121 | MCU_R5FSS0_CORE0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_268 | C7X256V0_CLEC | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_268 | C7X256V1_CLEC | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | TIFS0_nvic_IN_113 | TIFS0 | MCASP0 interrupt request | level |
MCASP0 | MCASP0_xmit_intr_pend_0 | HSM0_nvic_IN_113 | HSM0 | MCASP0 interrupt request | level |
MCASP1 | MCASP1_rec_dma_event_req_0 | PDMA2_mcasp_main_1_rx_IN_0 | PDMA2 | MCASP1 interrupt request | pulse |
MCASP1 | MCASP1_rec_intr_pend_0 | GICSS0_spi_IN_269 | GICSS0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | R5FSS0_CORE0_intr_IN_122 | R5FSS0_CORE0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_122 | MCU_R5FSS0_CORE0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_269 | C7X256V0_CLEC | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_269 | C7X256V1_CLEC | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | TIFS0_nvic_IN_117 | TIFS0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_rec_intr_pend_0 | HSM0_nvic_IN_117 | HSM0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_dma_event_req_0 | PDMA2_mcasp_main_1_tx_IN_0 | PDMA2 | MCASP1 interrupt request | pulse |
MCASP1 | MCASP1_xmit_intr_pend_0 | GICSS0_spi_IN_270 | GICSS0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | R5FSS0_CORE0_intr_IN_123 | R5FSS0_CORE0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_123 | MCU_R5FSS0_CORE0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_270 | C7X256V0_CLEC | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_270 | C7X256V1_CLEC | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | TIFS0_nvic_IN_114 | TIFS0 | MCASP1 interrupt request | level |
MCASP1 | MCASP1_xmit_intr_pend_0 | HSM0_nvic_IN_114 | HSM0 | MCASP1 interrupt request | level |
MCASP2 | MCASP2_rec_dma_event_req_0 | PDMA2_mcasp_main_2_rx_IN_0 | PDMA2 | MCASP2 interrupt request | pulse |
MCASP2 | MCASP2_rec_intr_pend_0 | GICSS0_spi_IN_271 | GICSS0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | R5FSS0_CORE0_intr_IN_124 | R5FSS0_CORE0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_124 | MCU_R5FSS0_CORE0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_271 | C7X256V0_CLEC | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_271 | C7X256V1_CLEC | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | TIFS0_nvic_IN_118 | TIFS0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_rec_intr_pend_0 | HSM0_nvic_IN_118 | HSM0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_dma_event_req_0 | PDMA2_mcasp_main_2_tx_IN_0 | PDMA2 | MCASP2 interrupt request | pulse |
MCASP2 | MCASP2_xmit_intr_pend_0 | GICSS0_spi_IN_272 | GICSS0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | R5FSS0_CORE0_intr_IN_125 | R5FSS0_CORE0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_125 | MCU_R5FSS0_CORE0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_272 | C7X256V0_CLEC | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_272 | C7X256V1_CLEC | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | TIFS0_nvic_IN_115 | TIFS0 | MCASP2 interrupt request | level |
MCASP2 | MCASP2_xmit_intr_pend_0 | HSM0_nvic_IN_115 | HSM0 | MCASP2 interrupt request | level |
MCASP3 | MCASP3_rec_dma_event_req_0 | PDMA3_mcasp_main_3_rx_IN_0 | PDMA3 | MCASP3 interrupt request | pulse |
MCASP3 | MCASP3_rec_intr_pend_0 | MAIN_GPIOMUX_INTROUTER0_in_IN_186 | MAIN_GPIOMUX_INTROUTER0 | MCASP3 interrupt request | level |
MCASP3 | MCASP3_rec_intr_pend_0 | R5FSS0_CORE0_intr_IN_118 | R5FSS0_CORE0 | MCASP3 interrupt request | level |
MCASP3 | MCASP3_rec_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_118 | MCU_R5FSS0_CORE0 | MCASP3 interrupt request | level |
MCASP3 | MCASP3_xmit_dma_event_req_0 | PDMA3_mcasp_main_3_tx_IN_0 | PDMA3 | MCASP3 interrupt request | pulse |
MCASP3 | MCASP3_xmit_intr_pend_0 | MAIN_GPIOMUX_INTROUTER0_in_IN_187 | MAIN_GPIOMUX_INTROUTER0 | MCASP3 interrupt request | level |
MCASP3 | MCASP3_xmit_intr_pend_0 | R5FSS0_CORE0_intr_IN_117 | R5FSS0_CORE0 | MCASP3 interrupt request | level |
MCASP3 | MCASP3_xmit_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_117 | MCU_R5FSS0_CORE0 | MCASP3 interrupt request | level |
MCASP4 | MCASP4_rec_dma_event_req_0 | PDMA3_mcasp_main_4_rx_IN_0 | PDMA3 | MCASP4 interrupt request | pulse |
MCASP4 | MCASP4_rec_intr_pend_0 | MAIN_GPIOMUX_INTROUTER0_in_IN_188 | MAIN_GPIOMUX_INTROUTER0 | MCASP4 interrupt request | level |
MCASP4 | MCASP4_rec_intr_pend_0 | R5FSS0_CORE0_intr_IN_252 | R5FSS0_CORE0 | MCASP4 interrupt request | level |
MCASP4 | MCASP4_rec_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_252 | MCU_R5FSS0_CORE0 | MCASP4 interrupt request | level |
MCASP4 | MCASP4_xmit_dma_event_req_0 | PDMA3_mcasp_main_4_tx_IN_0 | PDMA3 | MCASP4 interrupt request | pulse |
MCASP4 | MCASP4_xmit_intr_pend_0 | MAIN_GPIOMUX_INTROUTER0_in_IN_189 | MAIN_GPIOMUX_INTROUTER0 | MCASP4 interrupt request | level |
MCASP4 | MCASP4_xmit_intr_pend_0 | R5FSS0_CORE0_intr_IN_251 | R5FSS0_CORE0 | MCASP4 interrupt request | level |
MCASP4 | MCASP4_xmit_intr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_251 | MCU_R5FSS0_CORE0 | MCASP4 interrupt request | level |
Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
---|---|---|---|---|
MCASP0 | AUX_CLK | MAIN_PLL2_HSDIV8_CLKOUT | MCASP0_CLKSEL[2:0] | |
MAIN_PLL1_HSDIV6_CLKOUT | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | MCASP0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | MCASP0_CLKSEL[2:0] | |||
MCASP_AHCLKR_PIN | EXT_REFCLK1 | MCASP0_AHCLKSEL[3:0] | ||
HFOSC0_CLKOUT | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_PBIST_CLK | MCASP0_AHCLKSEL[3:0] | |||
MAIN_SYSCLK0/2 | MCASP0_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[3:0] | |||
MCASP_AHCLKX_PIN | EXT_REFCLK1 | MCASP0_AHCLKSEL[11:8] | ||
HFOSC0_CLKOUT | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_PBIST_CLK | MCASP0_AHCLKSEL[11:8] | |||
MAIN_SYSCLK0/2 | MCASP0_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP0_AHCLKSEL[11:8] | |||
ICLK | MAIN_SYSCLK0/2 | MCASP0 Interface Clock | ||
MCASP1 | AUX_CLK | MAIN_PLL2_HSDIV8_CLKOUT | MCASP1_CLKSEL[2:0] | |
MAIN_PLL1_HSDIV6_CLKOUT | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP1_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | MCASP1_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | MCASP1_CLKSEL[2:0] | |||
MCASP_AHCLKR_PIN | EXT_REFCLK1 | MCASP1_AHCLKSEL[3:0] | ||
HFOSC0_CLKOUT | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_PBIST_CLK | MCASP1_AHCLKSEL[3:0] | |||
MAIN_SYSCLK0/2 | MCASP1_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[3:0] | |||
MCASP_AHCLKX_PIN | EXT_REFCLK1 | MCASP1_AHCLKSEL[11:8] | ||
HFOSC0_CLKOUT | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_PBIST_CLK | MCASP1_AHCLKSEL[11:8] | |||
MAIN_SYSCLK0/2 | MCASP1_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP1_AHCLKSEL[11:8] | |||
ICLK | MAIN_SYSCLK0/2 | MCASP1 Interface Clock | ||
MCASP2 | AUX_CLK | MAIN_PLL2_HSDIV8_CLKOUT | MCASP2_CLKSEL[2:0] | |
MAIN_PLL1_HSDIV6_CLKOUT | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP2_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | MCASP2_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | MCASP2_CLKSEL[2:0] | |||
MCASP_AHCLKR_PIN | EXT_REFCLK1 | MCASP2_AHCLKSEL[3:0] | ||
HFOSC0_CLKOUT | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_PBIST_CLK | MCASP2_AHCLKSEL[3:0] | |||
MAIN_SYSCLK0/2 | MCASP2_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[3:0] | |||
MCASP_AHCLKX_PIN | EXT_REFCLK1 | MCASP2_AHCLKSEL[11:8] | ||
HFOSC0_CLKOUT | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_PBIST_CLK | MCASP2_AHCLKSEL[11:8] | |||
MAIN_SYSCLK0/2 | MCASP2_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP2_AHCLKSEL[11:8] | |||
ICLK | MAIN_SYSCLK0/2 | MCASP2 Interface Clock | ||
MCASP3 | AUX_CLK | MAIN_PLL2_HSDIV8_CLKOUT | MCASP3_CLKSEL[2:0] | |
MAIN_PLL1_HSDIV6_CLKOUT | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP3_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | MCASP3_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | MCASP3_CLKSEL[2:0] | |||
MCASP_AHCLKR_PIN | EXT_REFCLK1 | MCASP3_AHCLKSEL[3:0] | ||
HFOSC0_CLKOUT | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_PBIST_CLK | MCASP3_AHCLKSEL[3:0] | |||
MAIN_SYSCLK0/2 | MCASP3_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[3:0] | |||
MCASP_AHCLKX_PIN | EXT_REFCLK1 | MCASP3_AHCLKSEL[11:8] | ||
HFOSC0_CLKOUT | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_PBIST_CLK | MCASP3_AHCLKSEL[11:8] | |||
MAIN_SYSCLK0/2 | MCASP3_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP3_AHCLKSEL[11:8] | |||
ICLK | MAIN_SYSCLK0/2 | MCASP3 Interface Clock | ||
MCASP4 | AUX_CLK | MAIN_PLL2_HSDIV8_CLKOUT | MCASP4_CLKSEL[2:0] | |
MAIN_PLL1_HSDIV6_CLKOUT | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | MCASP4_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | MCASP4_CLKSEL[2:0] | |||
MAIN_SYSCLK0/2 | MCASP4_CLKSEL[2:0] | |||
MCASP_AHCLKR_PIN | EXT_REFCLK1 | MCASP4_AHCLKSEL[3:0] | ||
HFOSC0_CLKOUT | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_PBIST_CLK | MCASP4_AHCLKSEL[3:0] | |||
MAIN_SYSCLK0/2 | MCASP4_AHCLKSEL[3:0] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[3:0] | |||
MCASP_AHCLKX_PIN | EXT_REFCLK1 | MCASP4_AHCLKSEL[11:8] | ||
HFOSC0_CLKOUT | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_PLL2_HSDIV8_CLKOUT | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL5_HSDIV1_CLKOUT | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV7_CLKOUT | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
EXT_REFCLK1 | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_AWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ATL_BWS0_SEL[3:0] | ||||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_PBIST_CLK | MCASP4_AHCLKSEL[11:8] | |||
MAIN_SYSCLK0/2 | MCASP4_AHCLKSEL[11:8] | |||
MAIN_TIEOFF0 | MCASP4_AHCLKSEL[11:8] | |||
ICLK | MAIN_SYSCLK0/2 | MCASP4 Interface Clock |