The DDR subsystem in this device comprises
DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR
subsystem is referred to as DDRSS0 and is used to provide an interface to external SDRAM
devices which can be utilized for storing program or data. DDRSS0 is accessed via CBASS0
interconnect.
The DDRSS0 supports:
- Memory Types:
- LPDDR4 up to @ 0.75V or 0.85V
VDD_CORE
- Memory Bus Features:
- Up to 32-bit width with in-line
ECC
- Up to 2 ranks
- LPDDR4 densities up to 8GBytes
(4GBytes each rank)
- Two System Bus Interfaces - one for
real time and another for non-real time traffic:
- 256-bit data width
- Little endian only
- Address aliasing prevention to
block accesses to unpopulated SDRAM region
- Clock asynchronous to DDR
clock
- Configuration Bus Interface:
- 32-bit data width
- Linear incrementing addressing
mode
- 32-bit aligned accesses only
- Little endian only
- Clock asynchronous to DDR
clock
- Key Features:
- Full coherency across all
commands
- Bank interleaving
- Priority based scheduling
- Scheduling based on bank
openness
- Class of Service (CoS) - Three
latency classes supported
- Leaky bucket function to avoid
blocking of Low Priority Thread
- Drain function to expedite
execution of reads in the controller
- Read/write scheduling to avoid
turn-around time
- Prioritized refresh scheduling
- Dynamic change of refresh rate via
software for extended temperatures
- Statistical counters for
performance management
- SDRAM ECC Features:
- In-line ECC
- 64-byte ECC calculated over
512-byte data
- Read-modify-write ECC for sub-word
writes
- Support ECC cache to improve
in-line ECC performance
- Support 64 cache-lines each
512-byte wide
- In-line ECC performance impact
shall be minimum of 12.5% for linear cached traffic
- ECC address error logging
- Statistical counters for counting
ECC errors
- Low Power Features:
- All power modes defined by JEDEC
(clock stop for LPDDR4, self-refresh, power-down, etc.)
- Self-refresh entry and exit via
software or hardware clock stop request/acknowledge
- System bus clock stop via hardware
clock stop request/acknowledge when controller is idle
- Automatic idle power saving mode
when no or low activity is detected
- DDR and system bus clock frequency
change using self-refresh via software or hardware clock stop
request/acknowledge
- Turning off SoC power after DDR is
put into self-refresh (DDR reset and CKE I/O retention)
- Tri-stating of all DDR I/O cells
via software while driving CKE and RESETn pins during self-refresh
- LPDDR4 Frequency Set Point
(FSP)
- Support power switches on DDR
subchip for low leakage power in low-power modesSupport power switches on DDR
subchip for low leakage power in low-power modes
- Functional Safety Features:
- VBUSM2AXI bridge AXI bus
timeout
- DDR4 command bus parity
- DDR PHY Features:
- Automatic and software controllable
initialization and calibration (ZQ) for the DDR PHY and I/O cells
- Automatic and software controllable
delay line calibrations with Voltage and Temperature (VT) compensation
- Automatic and software controllable
write levelling with VT compensation
- Automatic read DQS gate training
per rank with VT compensation
- Automatic and software controllable
DQ/DQS eye training per rank
- Automatic and software controllable
read and write data bit deskew
- Automatic and software controllable
Command/Address (CA) levelling with VT compensation for LPDDR4
- Automatic and software controllable
CA bit deskew for LPDDR4
- Refreshes to SDRAM during leveling
and training
- No seeding requirement based on
board topology for any of the leveling and training algorithms
- Dynamic/automatic I/O Receiver
disable when read transfer is not on going
- Capability of disabling data macros
and I/O cells when not in use