SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
MCRC Controller only generates one interrupt request to interrupt manager. An interrupt offset register (MCRC64_0_CRC_INT_OFFSET_REG) is provided to indicate the source of the pending interrupt with highest priority. Table 12-342 shows the offset interrupt vector address of each interrupt in an ascending order of priority.
Interrupt Condition | Offset Value |
---|---|
Phantom | 0x0 |
Ch1 CRC Fail | 0x1 |
Ch2 CRC Fail | 0x2 |
Ch3 CRC Fail | 0x3 |
Ch4 CRC Fail | 0x4 |
reserved | 0x5-0x8 |
Ch1 Compression Complete | 0x9 |
Ch2 Compression Complete | 0xA |
Ch3 Compression Complete | 0xB |
Ch4 Compression Complete | 0xC |
reserved | 0xD-0x10 |
Ch1 Overrun | 0x11 |
Ch2 Overrun | 0x12 |
Ch3 Overrun | 0x13 |
Ch4 Overrun | 0x14 |
reserved | 0x15-0x18 |
Ch1 Underrun | 0x19 |
Ch2 Underrun | 0x1A |
Ch3 Underrun | 0x1B |
Ch4 Underrun | 0x1C |
reserved | 0x1D-0x20 |
Ch1 Timeout | 0x21 |
Ch2 Timeout | 0x22 |
Ch3 Timeout | 0x23 |
Ch4 Timeout | 0x24 |