Each block within the VPAC subsystem receives its own clocking signal:
- MAIN_CLK is the operation clock for all
infrastructure modules, such as UTC/DRU, HTS, ECC Aggregator, INTD, etc.
- VISS0_CLK is the operation clock for the VISS and its sub-modules
- LDC0_CLK is the operation clock for the LDC module
- MSC_CLK is the operation clock for the MSC module
- NF_CLK is the operation clock for the NF module
For more details on the source of each clock at
SoC level, see VPAC Integration.