SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The DCC can be programmed to count down one time using single-shot mode. In this mode, the DCC stops operation when both COUNT0 and VALID0 reach 0.
At the end of one sequence in single-shot mode the DCC2_DCCGCTRL[3-0] DCCENA bitfield is set to disabled, which stops further counting. Single-shot mode is enabled from the DCC2_DCCGCTRL[11-8] SINGLESHOT bitfield.
At the end of one sequence in single-shot mode, if there is no error which stops counting, then the done status bit is set in the DCC2_DCCSTATUS[1] DONEFLG bitfield and a done interrupt DCC_x_INT is generated. Software must clear the done bit before restarting the counting.