SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
On-Chip debug resources are made available through three mechanisms:
DAP
Off-chip debug tools are able to access On-Chip debug resources via the JTAG interface when not in Boundary Scan mode (see below). A CoreSight™ Compliant DAP architecture provides access via a DP and a collection of APs:
Table 13-4 describes the APSEL assignment for this device.
APSEL | AP | Description |
---|---|---|
0 | Config-AP | TI AP - Reserved |
1 | APB-AP | Provides access to Debug Config Plane |
2 | AXI-AP | Provides access to SoC Address Space |
3 | Power-AP | TI AP - Extended Power/Reset/Clock Control |
4-5 | Reserved | Reserved for future use |
6 | SEC-AP | TI AP - Authentication Interface |
10-31 | Reserved | Reserved for future use |
Boundary Scan
This device supports boundary scan using an IEEE 1149.1 compliant JTAG TAP that is made visible through the use of a compliance-enable mode (see Section 13.3.4). IEEE 1149.1 and 1149.6 Boundary Scan support are defined in device-specific BSDL files that can be found in the respective device’s product folder on ti.com.
SoC Address Space
The device architecture provides access to On-Chip debug resources through the SoC Address Space. This includes access to all DAP Access Ports (APs) as well as the Debug-APB address space.