SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each Interrupt Core (N = 0) has its own MMR interface with its own independent memory map
Address Offset | Register |
---|---|
0x00 | Revision Register |
0x04 | Info Register |
0x08 | Prioritized IRQ |
0x0C | Prioritized FIQ |
0x10 | IRQ Group Status |
0x14 | FIQ Group Status |
0x18 | IRQ Vector Address |
0x1C | FIQ Vector Address |
0x20 | Active IRQ |
0x24 | Active FIQ |
0x28-0x2F | Reserved |
0x30 | DED Vector Address |
0x34-0x1FF | Reserved |
0x400 + M*0x20 + 0x00 | Group M Interrupt Raw Status/Set Register |
0x400 + M*0x20 + 0x04 | Group M Interrupt Enabled Status/Clear Register |
0x400 + M*0x20 + 0x08 | Group M Interrupt Enabled Set Register |
0x400 + M*0x20 + 0x0C | Group M Interrupt Enabled Clear Register |
0x400 + M*0x20 + 0x10 | Group M Interrupt IRQ Enabled Status/Clear Register |
0x400 + M*0x20 + 0x14 | Group M Interrupt FIQ Enabled Status/Clear Register |
0x400 + M*0x20 + 0x18 | Group M Interrupt Map Register |
0x400 + M*0x20 + 0x1C | Group M Type Map Register |
0x1000 + Q*0x4 – 00x1FFF | Interrupt Q Priority Register |
0x2000 + Q*0x4 – 0x2FFF | Interrupt Q Vector Register |
There are M interrupt groups (0 through num_groups-1) with 32 interrupts per group.
There are Q interrupt inputs where Q = M * 32.
Accesses to the Interrupt Q Vector Register (Base Address + 0x2000 + Q*0x4) must be word-aligned, 32-bit accesses. Any write received with no bytes enabled will be ignored. Any writes receive with all bytes enabled will be executed. Any other write will not execute and will return an error status of Addressing Error.