The Display Subsystem IP module supports the following features:
- Two display outputs (for a single DSS7_UL instance)2
- Up to 24-bit per pixel parallel or embedded sync output
- Up to 300MHz pixel clock
- Support for RGB/YUV422 modes
- Support for progressive/interlaced modes
- Two input display processing pipelines
- One video pipeline supporting full RGB and 8/10-bit YUV data formats
with 3/5-tap 16-phase scaler capable of 0.25x to 16x resizing.
- One video_lite pipeline supporting full RGB and 8/10-bit YUV data
formats (no resizing support)
- Two Overlay Managers with multi layer alpha blending
- One DMA controller capable of supporting up to 2K input source width.
- 48bit addressing (256 TB reach)
- On-the-fly X/Y-axis flip of the source (Flip/Mirror mode support)
- Safety check (freeze frame detection and data correctness check)