CPSW0 |
CPPI_CLK |
MAIN_SYSCLK0/2 |
|
CPSW0 CPPI packet streaming interface clock |
CPTS_RFT_CLK |
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
GMII1_MR_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/10 |
|
|
GMII1_MT_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/10 |
|
|
GMII2_MR_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/10 |
|
|
GMII2_MT_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/10 |
|
|
GMII_RFT_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/2 |
|
CPSW0 125MHz Gigabit Mode Clock |
RGMII_MHZ_250_CLK |
MAIN_PLL2_HSDIV1_CLKOUT |
|
CPSW0 250-MHz Reference clock |
RGMII_MHZ_50_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/5 |
|
CPSW0 50-MHz Reference Clock |
RGMII_MHZ_5_CLK |
MAIN_PLL2_HSDIV1_CLKOUT/50 |
|
CPSW0 5-MHz Reference Clock |
SERDES1_REFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL2_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV5_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
SERDES1_RXCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL2_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV5_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
SERDES1_RXFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL2_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV5_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
SERDES1_TXFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL2_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV5_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
SERDES1_TXMCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL2_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV5_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
PCIE0_CLKSEL[2:0] |
|
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
PCIE0_CLKSEL[2:0] |
|
HFOSC0_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
PCIE0_CLKSEL[2:0] |
|
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/4 |
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK/2 |
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PBIST_CLK |
|
|
SERDES2_REFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
|
|
MAIN_SYSCLK0/4 |
|
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
|
|
MAIN_PBIST_CLK/4 |
|
|
MAIN_PBIST_CLK/2 |
|
|
SERDES2_RXCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
|
|
MAIN_SYSCLK0/4 |
|
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
|
|
MAIN_PBIST_CLK/4 |
|
|
MAIN_PBIST_CLK/2 |
|
|
SERDES2_RXFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
|
|
MAIN_SYSCLK0/4 |
|
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
|
|
MAIN_PBIST_CLK/4 |
|
|
MAIN_PBIST_CLK/2 |
|
|
SERDES2_TXFCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
|
|
MAIN_SYSCLK0/4 |
|
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
|
|
MAIN_PBIST_CLK/4 |
|
|
MAIN_PBIST_CLK/2 |
|
|
SERDES2_TXMCLK |
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT_SERDES |
SERDES0_CLKSEL[1:0] |
|
EXT_REFCLK1 |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
SERDES0_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PLL1_HSDIV6_CLKOUT/4 |
|
|
MAIN_SYSCLK0/4 |
|
|
MAIN_SYSCLK0/2 |
|
|
MAIN_PBIST_CLK |
|
|
MAIN_PLL2_HSDIV5_CLKOUT |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
CPSW_CLKSEL[2:0] |
|
HFOSC0_CLKOUT_SERDES |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL2_HSDIV0_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_PLL0_HSDIV9_CLKOUT |
CPSW_CLKSEL[2:0] |
|
SERDES1_CLKSEL[1:0] |
|
MAIN_SYSCLK0/2 |
CPSW_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL0_HSDIV6_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CP_GEMAC_CPTS_REF_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_EXT_REFCLK0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
EXT_REFCLK1 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
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MAIN_PLL2_HSDIV1_CLKOUT/10 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
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MAIN_PLL2_HSDIV1_CLKOUT/2 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/5 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PLL2_HSDIV1_CLKOUT/50 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TAP_BS_JTAG__CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MCU_DFT_SCAN_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
MAIN_TIEOFF0 |
CPSW_CLKSEL[2:0] |
|
PCIE0_CLKSEL[2:0] |
|
CLK_12M_RC |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_PBIST_CLK |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0 |
CPSW_CLKSEL[2:0] |
|
MAIN_SYSCLK0/4 |
|
|
HFOSC0_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_PLL0_HSDIV8_CLKOUT |
USB1_CLKSEL[0:0] |
|
MAIN_TAP_BS_JTAG__CLK |
|
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MAIN_PBIST_CLK/4 |
|
|
MAIN_PBIST_CLK/2 |
|
|