SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Figure 12-335 shows all of the MCASP interface signals.
i represents a MCASP instance. See the device datasheet for available domains and MCASP instances.
n represents a AXR signal from a MCASP instance. See the device datasheet for available domains and MCASP instances.
Table 12-264 describes the MCASP I/O signals.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
MCASPi(3) module | ||||
AXR0 | MCASPi(3)_AXR0 | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | MCASPi(3)_AXR1 | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | MCASPi(3)_AXR2 | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | MCASPi(3)_AXR3 | I/O | Audio transmit/receive data - channel 3 | HiZ |
AXR4 | MCASPi(3)_AXR4 | I/O | Audio transmit/receive data - channel 4 | HiZ |
AXR5 | MCASPi(3)_AXR5 | I/O | Audio transmit/receive data - channel 5 | HiZ |
AXR6 | MCASPi(3)_AXR6 | I/O | Audio transmit/receive data - channel 6 | HiZ |
AXR7 | MCASPi(3)_AXR7 | I/O | Audio transmit/receive data - channel 7 | HiZ |
AXR8 | MCASPi(3)_AXR8 | I/O | Audio transmit/receive data - channel 8 | HiZ |
AXR9 | MCASPi(3)_AXR9 | I/O | Audio transmit/receive data - channel 9 | HiZ |
AXR10 | MCASPi(3)_AXR10 | I/O | Audio transmit/receive data - channel 10 | HiZ |
AXR11 | MCASPi(3)_AXR11 | I/O | Audio transmit/receive data - channel 11 | HiZ |
AXR12 | MCASPi(3)_AXR12 | I/O | Audio transmit/receive data - channel 12 | HiZ |
AXR13 | MCASPi(3)_AXR13 | I/O | Audio transmit/receive data - channel 13 | HiZ |
AXR14 | MCASPi(3)_AXR14 | I/O | Audio transmit/receive data - channel 14 | HiZ |
AXR15 | MCASPi(3)_AXR15 | I/O | Audio transmit/receive data - channel 15 | HiZ |
ACLKX | MCASPi(3)_ACLKX | I/O | Transmit bit clock | HiZ |
AFSX | MCASPi(3)_AFSX | I/O | Transmit frame synchronization | HiZ |
ACLKR | MCASPi(3)_ACLKR | I/O | Receive bit clock | HiZ |
AFSR | MCASPi(3)_AFSR | I/O | Receive frame synchronization | HiZ |
MCASPi(3)_AHCLKX_I/O | AUDIO_EXT_REFCLK[0-1] | I/O | Transmit high-frequency controller clock. See Module Integration | HiZ |
MCASPi(3)_AHCLKR_I/O | AUDIO_EXT_REFCLK[0-1] | I/O | Receive high-frequency controller clock. See Module Integration | HiZ |
MCASPi_AHCLKR_I/O and MCASPi_AHCLKX_I/O signals are multiplexed to AUDIO_EXT_REFCLK[0-1] device pins.
For MCASPi_ACLKR_I/O, MCASPi_ACLKX_I/O, MCASPi_AHCLKR_I/O and MCASPi_AHCLKX_I/O signals to work properly, the RXACTIVE bit of the appropriate CTRLMMR_PADCONFIGy registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.
A serializer AXR data pin is shared between the transmit and receive logic of that serializer. The direction of data is determined in the MCASP_PDIR register and the function (Tx or Rx) is selected in the corresponding serializer control register MCASP_SRCTLn (n = 0 to 15).