SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
ROM code must be aware of the reference clock provided to PLLs. That is, the speed of the quartz crystal, or the clock supplied by an external clock oscillator. On how to indicate the PLL reference clock, see PLL Reference Clock Selection
ROM code configures only PLLs which are required during boot. Therefore, if a PLL is required for the backup boot mode but not the primary boot mode, and if the backup boot mode never executes, then the PLLs required for backup boot are not enabled.
The following tables show the HSDIV values that are programmed by the R5 ROM if a boot mode uses it. A value of NA means that the ROM does not program that HSDIV
PLL POSTDIV | HSDIV | Value | Frequency(MHz) | Boot Peripheral/IP |
---|---|---|---|---|
0 | HSDIV0 | 4 | 500 | MAIN SYSCLK0 |
0 | HSDIV1 | 10 | 200 | OSPI |
0 | HSDIV2 | 0 | NA | WKUP_CLKOUT |
0 | HSDIV3 | 15 | 133 | GPMC NOR/GPMC NAND |
0 | HSDIV4 | 0 | NA | MCAN |
1 | HSDIV5 | 5 | 200 | eMMC0 |
1 | HSDIV6 | 0 | NA | CPTS |
1 | HSDIV7 | 4 | 250 | TIMER |
1 | HSDIV8 | 0 | NA | USB0 |
1 | HSDIV9 | 0 | NA | PRUSS-M |
PLL POSTDIV | HSDIV | Value | Frequency(MHz) | Boot Peripheral/IP |
---|---|---|---|---|
0 | HSDIV0 | 10 | 192 | UART |
0 | HSDIV1 | 12 | 160 | UART |
0 | HSDIV2 | 0 | NA | WKUP_CLKOUT |
0 | HSDIV3 | 0 | NA | TIMER |
0 | HSDIV4 | 0 | NA | Reserved |
1 | HSDIV5 | 0 | NA | OSPI |
1 | HSDIV6 | 0 | NA | McASP |
PLL POSTDIV | HSDIV | Value | Frequency(MHz) | Boot Peripheral/IP |
---|---|---|---|---|
0 | HSDIV0 | 0 | NA | PRUSS-M core |
0 | HSDIV1 | 8 | 250 | CP_GEMAC |
0 | HSDIV2 | 10 | 200 | eMMC1 |
0 | HSDIV3 | 0 | NA | DebugSS |
0 | HSDIV4 | 0 | NA | GPU |
1 | HSDIV5 | 0 | NA | PRUSS-M IEP |
1 | HSDIV6 | 0 | NA | TIMER |
1 | HSDIV7 | 0 | NA | GPMC |
1 | HSDIV8 | 0 | NA | McASP |
1 | HSDIV9 | 0 | NA | WKUP_CLKOUT |
HSDIV | Value | Frequency(MHz) | Boot Peripheral/IP |
---|---|---|---|
HSDIV0 | 5 | 400 | HSM/SMS |
HSDIV1 | 5 | 400 | SA3_UL PKA |
HSDIV5 | 3 | 800 | DM |