SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each timer can send or receive stimulus to/from the external (off-chip) system. In the device all timers are configured to output a PWM pulse or receive an external event signal used as a trigger to capture the current timer count.
Figure 12-413 shows the external system interface for the timers, and Table 12-325 describes the timer inputs and outputs.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
MCU_TIMERi(2) | ||||
MCU_TIMER_IOi(2) | MCU_TIMERi(2)_PIEVENTCAPT | I/O | MCU_TIMERi(2) trigger input or | 0 |
MCU_TIMERi(2)_POTIMERPWM | MCU_TIMERi(2) output | |||
TIMERi(2) | ||||
TIMER_IOi(2) | TIMERi(2)_PIEVENTCAPT | I/O | TIMERi(2) trigger input or | 0 |
TIMERi(2)_POTIMERPWM | TIMERi(2) PWM output |
Each MCU_TIMER_PO_GPOCFG and TIMER_PO_GPOCFG signals are used as an output enable to control the function of the MCU_TIMER_IO[3-0], and respectively TIMER_IO[11-0], as the PWM output (PO_GPOCFG = 0) or capture input (PO_GPOCFG = 1).
For more information about device level signals (pull-up/down resistors, buffer type, and others), see tables Pin Attributes in the device-specific Datasheet.