SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | dependences |
---|---|---|---|---|---|---|---|
SERDES_10G0 | PSC0 | GP_CORE | LPSC_MAIN_SERDES0 | 40 | OFF | YES | LPSC_MAIN_IP |
SERDES_10G1 | PSC0 | GP_CORE | LPSC_MAIN_SERDES1 | 41 | OFF | YES | LPSC_MAIN_IP |
Module Instance | Source | Description |
---|---|---|
SERDES_10G0 | 0 | NONE |
SERDES_10G1 | 0 | NONE |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | GICSS0_spi_IN_167 | GICSS0 | SERDES_10G0 interrupt request | level |
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | R5FSS0_CORE0_intr_IN_166 | R5FSS0_CORE0 | SERDES_10G0 interrupt request | level |
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | WKUP_R5FSS0_CORE0_intr_IN_166 | WKUP_R5FSS0_CORE0 | SERDES_10G0 interrupt request | level |
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_166 | MCU_R5FSS0_CORE0 | SERDES_10G0 interrupt request | level |
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | C7X256V0_CLEC_gic_spi_IN_167 | C7X256V0_CLEC | SERDES_10G0 interrupt request | level |
SERDES_10G0 | SERDES_10G0_phy_pwr_timeout_lvl_0 | C7X256V1_CLEC_gic_spi_IN_167 | C7X256V1_CLEC | SERDES_10G0 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | GICSS0_spi_IN_119 | GICSS0 | SERDES_10G1 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | R5FSS0_CORE0_intr_IN_154 | R5FSS0_CORE0 | SERDES_10G1 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | WKUP_R5FSS0_CORE0_intr_IN_53 | WKUP_R5FSS0_CORE0 | SERDES_10G1 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | MCU_R5FSS0_CORE0_cpu0_intr_IN_154 | MCU_R5FSS0_CORE0 | SERDES_10G1 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | C7X256V0_CLEC_gic_spi_IN_119 | C7X256V0_CLEC | SERDES_10G1 interrupt request | level |
SERDES_10G1 | SERDES_10G1_phy_pwr_timeout_lvl_0 | C7X256V1_CLEC_gic_spi_IN_119 | C7X256V1_CLEC | SERDES_10G1 interrupt request | level |
Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
---|---|---|---|---|
SERDES_10G0 | CLK | MAIN_SYSCLK0/4 | ||
CORE_REF_CLK | HFOSC0_CLKOUT_SERDES | SERDES0_CLKSEL[1:0] | ||
EXT_REFCLK1 | SERDES0_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES0_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES0_CLKSEL[1:0] | |||
IP1_LN0_TXCLK | MAIN_SYSCLK0/2 | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | ||||
MAIN_SYSCLK0/4 | ||||
MAIN_SYSCLK0/4 | ||||
HFOSC0_CLKOUT_SERDES | SERDES0_CLKSEL[1:0] | |||
EXT_REFCLK1 | SERDES0_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES0_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES0_CLKSEL[1:0] | |||
MAIN_SYSCLK0/2 | ||||
MAIN_PBIST_CLK | ||||
MAIN_PLL2_HSDIV5_CLKOUT | CPSW_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | CPSW_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/5 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/50 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CLK_12M_RC | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0 | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | ||||
HFOSC0_CLKOUT | USB1_CLKSEL[0:0] | |||
MAIN_PLL0_HSDIV8_CLKOUT | USB1_CLKSEL[0:0] | |||
MAIN_TAP_BS_JTAG__CLK | ||||
MAIN_PBIST_CLK/4 | ||||
MAIN_PBIST_CLK/2 | ||||
IP2_LN0_TXCLK | MAIN_SYSCLK0/2 | |||
MAIN_PBIST_CLK | ||||
MAIN_PLL2_HSDIV5_CLKOUT | CPSW_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | CPSW_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/5 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/50 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
HFOSC0_CLKOUT_SERDES | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
HFOSC0_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CLK_12M_RC | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0 | CPSW_CLKSEL[2:0] | |||
IP3_LN0_TXCLK | MAIN_TIEOFF0 | |||
IP4_LN0_TXCLK | MAIN_TIEOFF0 | |||
TAP_TCK | MAIN_TAP_BS_JTAG__CLK | |||
TFT_FAST_CLK | MCU_DFT_SCAN_CLK | |||
SERDES_10G1 | CLK | MAIN_SYSCLK0/4 | ||
CORE_REF_CLK | HFOSC0_CLKOUT_SERDES | SERDES1_CLKSEL[1:0] | ||
EXT_REFCLK1 | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL2_HSDIV0_CLKOUT | SERDES1_CLKSEL[1:0] | |||
MAIN_PLL0_HSDIV9_CLKOUT | SERDES1_CLKSEL[1:0] | |||
IP1_LN0_TXCLK | MAIN_SYSCLK0/2 | |||
MAIN_PLL2_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV5_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_SYSCLK0 | PCIE0_CLKSEL[2:0] | |||
CPSW_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/10 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/5 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV1_CLKOUT/50 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | PCIE0_CLKSEL[2:0] | |||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | PCIE0_CLKSEL[2:0] | |||
MAIN_PLL1_HSDIV6_CLKOUT/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MCU_DFT_SCAN_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | PCIE0_CLKSEL[2:0] | |||
HFOSC0_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | PCIE0_CLKSEL[2:0] | |||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/4 | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK/2 | PCIE0_CLKSEL[2:0] | |||
CLK_12M_RC | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | PCIE0_CLKSEL[2:0] | |||
MAIN_TIEOFF0 | PCIE0_CLKSEL[2:0] | |||
IP2_LN0_TXCLK | MAIN_SYSCLK0/2 | |||
MAIN_PBIST_CLK | ||||
MAIN_PLL2_HSDIV5_CLKOUT | CPSW_CLKSEL[2:0] | |||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
HFOSC0_CLKOUT_SERDES | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | CPSW_CLKSEL[2:0] | |||
SERDES1_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | CPSW_CLKSEL[2:0] | |||
MAIN_PLL2_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL0_HSDIV6_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CP_GEMAC_CPTS_REF_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_EXT_REFCLK0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/10 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/5 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL2_HSDIV1_CLKOUT/50 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
HFOSC0_CLKOUT_SERDES | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
EXT_REFCLK1 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL2_HSDIV0_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_PLL0_HSDIV9_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
SERDES0_CLKSEL[1:0] | ||||
MAIN_SYSCLK0/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PLL1_HSDIV6_CLKOUT/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MCU_DFT_SCAN_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_SYSCLK0/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
HFOSC0_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
USB1_CLKSEL[0:0] | ||||
MAIN_PLL0_HSDIV8_CLKOUT | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
USB1_CLKSEL[0:0] | ||||
MAIN_TAP_BS_JTAG__CLK | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK/4 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_PBIST_CLK/2 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
MAIN_TIEOFF0 | CPSW_CLKSEL[2:0] | |||
PCIE0_CLKSEL[2:0] | ||||
CLK_12M_RC | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_PBIST_CLK | CPSW_CLKSEL[2:0] | |||
MAIN_SYSCLK0 | CPSW_CLKSEL[2:0] | |||
IP3_LN0_TXCLK | MAIN_TIEOFF0 | |||
TAP_TCK | MAIN_TAP_BS_JTAG__CLK | |||
TFT_FAST_CLK | MCU_DFT_SCAN_CLK |