SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each channel can issue interrupt events.
Each interrupt event has status bits in the MCSPI_IRQSTATUS register (RXi_FULL, TXi_UNDERFLOW, TXi_EMPTY, etc.) (where x = 0, 3) that indicate whether service is required. Each status bit has an interrupt enable bit (a mask) in the MCSPI_IRQENABLE register (RXi_FULL_ENABLE, TXi_UNDERFLOW_ENABLE, TXi_EMPTY_ENABLE, etc.).
When an interrupt occurs and a mask is later applied on it, the interrupt line is not asserted again, even if the interrupt source is not serviced.
The MCSPI supports interrupt-driven and polling operations.