SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The PCIe core decodes all MSI and MSI-X messages received from the link and forwards them as a 32-bit write transaction on the AXI controller interface.
The destination address for MSI/MSI-X write transactions should be the ARM GIC. The GIC will process the write transaction and create an interrupt to the ARM Ax CPU core in the device.