The CLEC supports the following features:
- Supports software scalable event routing mechanism
- RAM-based interrupt event routing table
- Supports aggregation of incoming interrupt events from:
- SoC peripherals
- MSMC
- DRU
- C71SS
- Supports distribution of each aggregated interrupt event to one or more of the following:
- SoC (could be routed to the GIC externally)
- DRU
- A72SS
- C71SS
- Supports originating interrupt events through the following mechanisms:
- MMR writes to trigger new events
- Reporting errors detected by the CLEC
- 2048 input events
- 128 output events
- Can handle both level and pulse input interrupts
- SoC out interrupt is always level regardless of input interrupt type (pulse or level)
- Can be used for inter-processor communication
(IPC) between A72 and C71
- Shares SPI (shared peripheral interrupt) input events with GIC