SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes the DPHY_TX application fields from an environment point of view (external connections).
Table 12-411 describes the DPHY_TX signals when transmitting data from a DSI module, and Table 12-412 describes the DPHY_TX signals when transmitting data from a CSI_TX_IF module.
Device Level Signal | I/O(1) | Description |
---|---|---|
DSI_TXN0 | I/O | DPHY_TX0 Lane 0 Transmit Differential Data (Negative) |
DSI_TXP0 | I/O | DPHY_TX0 Lane 0 Transmit Differential Data (Positive) |
DSI_TXN1 | O | DPHY_TX0 Lane 1 Transmit Differential Data (Negative) |
DSI_TXP1 | O | DPHY_TX0 Lane 1 Transmit Differential Data (Positive) |
DSI_TXN2 | O | DPHY_TX0 Lane 2 Transmit Differential Data (Negative) |
DSI_TXP2 | O | DPHY_TX0 Lane 2 Transmit Differential Data (Positive) |
DSI_TXN3 | O | DPHY_TX0 Lane 3 Transmit Differential Data (Negative) |
DSI_TXP3 | O | DPHY_TX0 Lane 3 Transmit Differential Data (Positive) |
DSI_TXCLKN | O | DPHY_TX0 Transmit Differential Clock Lane (Negative) |
DSI_TXCLKP | O | DPHY_TX0 Transmit Differential Clock Lane (Positive) |
DSI_TXRCALIB | A | DPHY_TX0 pin for external calibration resistor. Refer to the device-specific Datasheet for a recommended resistor value. |
DSI_ATB_0_H | I/O | DPHY_TX0 Analog Test Bus 0 |
DSI_ATB_1_H | I/O | DPHY_TX0 Analog Test Bus 1 |
Device Level Signal | I/O | Description |
---|---|---|
CSI0_TXN0 | O | DPHY_TX0 Lane 0 Transmit Differential Data (Negative) |
CSI0_TXP0 | O | DPHY_TX0 Lane 0 Transmit Differential Data (Positive) |
CSI0_TXN1 | O | DPHY_TX0 Lane 1 Transmit Differential Data (Negative) |
CSI0_TXP1 | O | DPHY_TX0 Lane 1 Transmit Differential Data (Positive) |
CSI0_TXN2 | O | DPHY_TX0 Lane 2 Transmit Differential Data (Negative) |
CSI0_TXP2 | O | DPHY_TX0 Lane 2 Transmit Differential Data (Positive) |
CSI0_TXN3 | O | DPHY_TX0 Lane 3 Transmit Differential Data (Negative) |
CSI0_TXP3 | O | DPHY_TX0 Lane 3 Transmit Differential Data (Positive) |
CSI0_TXCLKN | O | DPHY_TX0 Transmit Differential Clock Lane (Negative) |
CSI0_TXCLKP | O | DPHY_TX0 Transmit Differential Clock Lane (Positive) |