SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
An active low asynchronous hardware reset is provided to CSI_RX_IF by device LPSC. It is internally resynchronized to the functional clock domain.
A software reset is triggered by configuring the CSI_RX_IF_VBUS2APB_SOFT_RESET bit-fields for protocol reset and/or module reset.