SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
There are multiple clocks from/to the physical interface. Figure 12-412 shows clocks used for the PHY clock domain logic (TXMCLK/TXFCLK) and for the return data clock (TXCLK). Not shown in the diagram are RX mode input clocks unused by EDP (TX only mode) – PHY_INn_RXCLK/RXFCLK/REFCLK.