TMS470MF06607

The TMS470MF06607 device is a member of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency ARM Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The TMS470MF06607 device contains the following:

• 16/32-Bit RISC CPU Core
• 640K-Byte Total Flash with SECDED ECC
  • 512K-Byte Program Flash
  • 128K- Byte Flash for additional program space or EEPROM Emulation
• 64K-Byte Static RAM (SRAM) with SECDED ECC
• Real-Time Interrupt Timer (RTI)
• Vectored Interrupt Module (VIM)
• Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST)
• 64-bit Cyclic Redundancy Checker (CRC)
• Frequency-Modulated Zero-Pin Phase-Locked Loop (FMZPLL)-Based Clock Module With Prescaler
• Two Multi-buffered Serial Peripheral Interfaces (MibSPI)
• Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)
• Two CAN Controller (DCAN)
• High-End Timer (HET)
• External Clock Prescale (ECP) Module
• One 16-Channel 10-Bit Multi-Buffered ADC (MibADC)
• Error Signaling Module (ESM)
• Four Dedicated General-Purpose I/O (GIO) Pins and 47 (2 of them are muxed with JTAG pins) Additional Peripheral I/Os (100-Pin Package)

The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space.