Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner


Product details


Function Dual-loop PLL Number of outputs 14 Number of Inputs 3 RMS jitter 0.088 Output frequency (Min) (MHz) 0.001 Output frequency (Max) (MHz) 3200 Input type LVCMOS, LVDS, LVPECL Output type LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.3 Features JESD204B Operating temperature range (C) -55 to 105 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (NKD) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers


  • EP Features
    • Gold Bondwires
    • Temperature Range: –55 to +105 °C
    • Lead Finish SnPb
  • Maximum Distribution Frequency: 3.2 GHz
  • JESD204B Support
  • Ultra-Low RMS Jitter
    • 88-fs RMS Jitter (12 kHz to 20 MHz)
    • 91-fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks From PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.2 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2
  • Up to 1 Buffered VCXO/Crystal Output From PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switchover Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (Even and Odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

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The LMK04828-EP device is the industry’s highest performance clock conditioner with JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay make the LMK04828-EP ideal for providing flexible high-performance clocking trees.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner datasheet Apr. 03, 2017
Application notes Multi-Clock Synchronization Dec. 30, 2019
Technical articles Solving synchronization challenges in Industrial Ethernet Jul. 19, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SNAM148F.ZIP (175 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

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