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LMK05028

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Low-jitter dual-channel network synchronizer clock

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Data sheet

LMK05028

ACTIVE
Data sheet Order now

Product details

Function Clock network synchronizer Number of outputs 8 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 750 Input type LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.3 Supply voltage (max) (V) 3.6 Features I2C, Integrated EEPROM, Pin programmable, SPI Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 4
Function Clock network synchronizer Number of outputs 8 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 750 Input type LVCMOS, LVDS, LVPECL, XTAL Output type CML, HCSL, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.3 Supply voltage (max) (V) 3.6 Features I2C, Integrated EEPROM, Pin programmable, SPI Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 4
VQFN (RGC) 64 81 mm² 9 x 9
  • Two Independent PLL Channels Featuring:
    • Jitter: 150-fs RMS for Outputs ≥ 100 MHz
    • Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz
    • Hitless Switching: 50-ps Phase Transient With Phase Cancellation
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
    • Any Input to Any Output Frequency Translation
  • Four Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs With Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V or 2.5-V LVCMOS Output Formats
  • EEPROM/ROM for Custom Clocks on Power-Up(2)
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 750 MHz on Input and Output
    • XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
    • DCO Mode: < 1 ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
    • Zero Delay for Deterministic Phase Offset
    • Robust Clock Monitoring and Status
    • I2C or SPI Interface
  • Excellent Power Supply Noise Rejection (PSNR)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40°C to +85°C
  • Two Independent PLL Channels Featuring:
    • Jitter: 150-fs RMS for Outputs ≥ 100 MHz
    • Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz
    • Hitless Switching: 50-ps Phase Transient With Phase Cancellation
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
    • Any Input to Any Output Frequency Translation
  • Four Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs With Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V or 2.5-V LVCMOS Output Formats
  • EEPROM/ROM for Custom Clocks on Power-Up(2)
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 750 MHz on Input and Output
    • XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
    • DCO Mode: < 1 ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
    • Zero Delay for Deterministic Phase Offset
    • Robust Clock Monitoring and Status
    • I2C or SPI Interface
  • Excellent Power Supply Noise Rejection (PSNR)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40°C to +85°C

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The device’s low jitter and high PSNR reduce bit error rates (BER) in high-speed serial links.

The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize its outputs.

Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The device’s low jitter and high PSNR reduce bit error rates (BER) in high-speed serial links.

The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize its outputs.

Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.
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Technical documentation

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Type Title Date
* Data sheet LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM datasheet (Rev. A) PDF | HTML 10 Apr 2018
Third party documents Intel® Stratix® 10 SX SoC Development Kit User Guide 12 Apr 2019
Technical article How to achieve network synchronization clocks with TI digital PLLs 21 Jun 2018
More literature TI Network Synchronizer Clock Value Adds in Communications and Industrial Applic 12 Apr 2018
More literature ITU-T G.8262 Compliance Test Results for the LMK05028 Digital PLL Network 10 Apr 2018
User guide LMK05028 Registers 10 Apr 2018
EVM User's guide LMK05028EVM User's Guide 19 Jan 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK05028EVM — LMK05028 Network Clock Generator and Synchronizer Evaluation Module

The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)

User guide: PDF
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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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Simulation model

LMK05028 IBIS Model

SNAM222.ZIP (213 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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