The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and good hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The low jitter and high PSNR of the device reduce bit error rates (BER) in high-speed serial links.
The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize the outputs.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM datasheet (Rev. B) | PDF | HTML | Feb 14, 2025 |
| Third party document | Intel® Stratix® 10 SX SoC Development Kit User Guide | Apr 12, 2019 | ||
| Technical article | How to achieve network synchronization clocks with TI digital PLLs | PDF | HTML | Jun 21, 2018 | |
| Application note | TI Network Synchronizer Clock Value Adds in Communications and Industrial Applic | Apr 12, 2018 | ||
| User guide | LMK05028 Registers | Apr 10, 2018 | ||
| Application note | ITU-T G.8262 Compliance Test Results for the LMK05028 Digital PLL Network | Apr 10, 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
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