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Product details

Parameters

Function Clock network synchronizer Number of outputs 8 Number of Inputs 4 RMS jitter (fs) 0.15 Output frequency (Min) (MHz) 1.00E-06 Output frequency (Max) (MHz) 750 Input type LVCMOS, LVDS, LVPECL, XTAL Output type LVDS, CML, LVPECL, HCSL, LVCMOS Supply voltage (Min) (V) 3.3 Supply voltage (Max) (V) 3.6 Features Integrated EEPROM, I2C, SPI, Pin programmable Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • Two Independent PLL Channels Featuring:
    • Jitter: 150-fs RMS for Outputs ≥ 100 MHz
    • Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz
    • Hitless Switching: 50-ps Phase Transient With Phase Cancellation
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
    • Any Input to Any Output Frequency Translation
  • Four Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Eight Clock Outputs With Programmable Drivers
    • Up to Six Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V or 2.5-V LVCMOS Output Formats
  • EEPROM/ROM for Custom Clocks on Power-Up(2)
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 750 MHz on Input and Output
    • XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
    • DCO Mode: < 1 ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
    • Zero Delay for Deterministic Phase Offset
    • Robust Clock Monitoring and Status
    • I2C or SPI Interface
  • Excellent Power Supply Noise Rejection (PSNR)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40°C to +85°C

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Description

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The device’s low jitter and high PSNR reduce bit error rates (BER) in high-speed serial links.

The device has two PLL channels and generates up to eight output clocks with 150-fs RMS jitter. Each PLL domain can select from any four reference inputs to synchronize its outputs.

Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM datasheet (Rev. A) Apr. 10, 2018
Third party documents Intel® Stratix® 10 SX SoC Development Kit User Guide Apr. 12, 2019
Technical articles How to achieve network synchronization clocks with TI digital PLLs Jun. 21, 2018
Application note TI Network Synchronizer Clock Value Adds in Communications and Industrial Applic Apr. 12, 2018
Application note ITU-T G.8262 Compliance Test Results for the LMK05028 Digital PLL Network Apr. 10, 2018
User guide LMK05028 Registers Apr. 10, 2018
User guide LMK05028EVM User's Guide Jan. 19, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
399
Description

The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)

Features
  • Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
  • 4 clock inputs supporting hitless switching and holdover
  • 8 differential or 16 LVCMOS output clocks or combination of both 
  • On-chip EEPROM for custom start-up clock clocks
  • Flexible oscillator options: onboard XOs, TCXO, or (...)

Software development

APPLICATION SOFTWARE & FRAMEWORK Download
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Features
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.
SUPPORT SOFTWARE Download
SNAC072AF.ZIP (51145 KB)

Design tools & simulation

SIMULATION MODEL Download
SNAM222.ZIP (213 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

Ordering & quality

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  • Ongoing reliability monitoring

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