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LMX2571-EP

ACTIVE

Enhanced-product, 1.34-GHz, low-power, extreme-temperature RF synthesizer with FSK modulation

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Data sheet

LMX2571-EP

ACTIVE
Data sheet Order now

Product details

Frequency (max) (MHz) 1344 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -231 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -124 Features FSK modulation, Integer-boundary spurs (IBS) suppression, Integrated VCO, Wideband Current consumption (mA) 39 Integrated VCO Yes Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Lock time (µs) (typ) (s) 140
Frequency (max) (MHz) 1344 Frequency (min) (MHz) 10 Normalized PLL phase noise (dBc/Hz) -231 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -124 Features FSK modulation, Integer-boundary spurs (IBS) suppression, Integrated VCO, Wideband Current consumption (mA) 39 Integrated VCO Yes Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Lock time (µs) (typ) (s) 140
VQFN (RHH) 36 36 mm² 6 x 6
  • VID#: V62/21613-01XE
  • -55 °C to +125 °C Operating Temperature
  • Any Frequency From 10 MHz to 1344 MHz
  • Low Phase Noise and Spurs
    • –123 dBc/Hz at 12.5-kHz Offset at 480 MHz
    • –145 dBc/Hz at 1-MHz Offset at 480 MHz
    • Normalized PLL Noise Floor of –231 dBc/Hz
    • Spurious Better Than –75 dBc/Hz
  • New FastLock to Reduce Lock Time
  • A Novel Technique to Remove Integer Boundary Spurs
  • Integrated 5-V Charge Pump and Output Divider for External VCO Operation
  • 2-, 4-, and 8-Level or Arbitrary Level Direct Digital FSK Modulation
  • One TX/RX Output or Two Fanout Outputs
  • Low Current Consumption
    • 39-mA Typical Synthesizer Mode (Internal VCO)
    • 9-mA Typical PLL Mode (External VCO)
  • 24-Bit Fractional-N Delta Sigma Modulator
  • Functional Differences between LMX2571 vs LMX2571-EP
    • LMX2571-EP has no TrCtl Pin
    • LMX2571-EP has no OSCin* pin, Differential Mode, or Crystal Mode
  • VID#: V62/21613-01XE
  • -55 °C to +125 °C Operating Temperature
  • Any Frequency From 10 MHz to 1344 MHz
  • Low Phase Noise and Spurs
    • –123 dBc/Hz at 12.5-kHz Offset at 480 MHz
    • –145 dBc/Hz at 1-MHz Offset at 480 MHz
    • Normalized PLL Noise Floor of –231 dBc/Hz
    • Spurious Better Than –75 dBc/Hz
  • New FastLock to Reduce Lock Time
  • A Novel Technique to Remove Integer Boundary Spurs
  • Integrated 5-V Charge Pump and Output Divider for External VCO Operation
  • 2-, 4-, and 8-Level or Arbitrary Level Direct Digital FSK Modulation
  • One TX/RX Output or Two Fanout Outputs
  • Low Current Consumption
    • 39-mA Typical Synthesizer Mode (Internal VCO)
    • 9-mA Typical PLL Mode (External VCO)
  • 24-Bit Fractional-N Delta Sigma Modulator
  • Functional Differences between LMX2571 vs LMX2571-EP
    • LMX2571-EP has no TrCtl Pin
    • LMX2571-EP has no OSCin* pin, Differential Mode, or Crystal Mode

The LMX2571-EP device is a low-power, high-performance, wideband PLLatinum™ RF synthesizer that integrates a delta-sigma fractional N PLL, multiple core voltage-controlled oscillator (VCO), programmable output dividers and two output buffers. The VCO cores work up to 5.376 GHz resulting in continuous output frequency range of 10 MHz to 1344 MHz.

This synthesizer can also be used with an external VCO. To that end, a dedicated 5-V charge pump and an output divider are available for this configuration.

A unique programmable multiplier is also incorporated to help improve spurs, allowing the system to use every channel even if it falls on an integer boundary.

The output has an integrated SPDT switch that can be used as a transmit and receive switch in FDD radio application. Both outputs can also be turned on to provide 2 outputs at the same time.

The LMX2571-EP supports direct digital FSK modulation through programming or pins. Discrete level FSK, pulse shaping FSK, and analog FM modulation are supported.

A new FastLock technique can be used allowing the user to step from one frequency to the next in less than 1.5 ms even when an external VCO is used with a narrow band loop filter.

The LMX2571-EP device is a low-power, high-performance, wideband PLLatinum™ RF synthesizer that integrates a delta-sigma fractional N PLL, multiple core voltage-controlled oscillator (VCO), programmable output dividers and two output buffers. The VCO cores work up to 5.376 GHz resulting in continuous output frequency range of 10 MHz to 1344 MHz.

This synthesizer can also be used with an external VCO. To that end, a dedicated 5-V charge pump and an output divider are available for this configuration.

A unique programmable multiplier is also incorporated to help improve spurs, allowing the system to use every channel even if it falls on an integer boundary.

The output has an integrated SPDT switch that can be used as a transmit and receive switch in FDD radio application. Both outputs can also be turned on to provide 2 outputs at the same time.

The LMX2571-EP supports direct digital FSK modulation through programming or pins. Discrete level FSK, pulse shaping FSK, and analog FM modulation are supported.

A new FastLock technique can be used allowing the user to step from one frequency to the next in less than 1.5 ms even when an external VCO is used with a narrow band loop filter.
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* Data sheet LMX2571-EP Low-Power, High-Performance PLLatinum RF Synthesizer With FSK Modulation datasheet (Rev. B) PDF | HTML 01 Jun 2022
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 11 Apr 2025
Application brief Compilation of RF Synthesizer Resources PDF | HTML 22 Oct 2024
Technical article How to implement FM modulation PDF | HTML 03 Aug 2017
Application note Frequency Shift Keying with LMX2571 30 May 2017
Application note LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs 12 Jan 2016
Technical article Timing is Everything: Improving integer boundary spurs in fractional PLL synthesiz PDF | HTML 05 Aug 2015

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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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