The LMX2492/92-Q1 is a low noise 14 GHz wideband delta-sigma fractional N PLL with ramp and chirp generation. It consists of a phase frequency detector, programmable charge pump, and high frequency input for the external VCO. The LMX2492/92-Q1 supports a broad and flexible class of ramping capabilities, including FSK, PSK, and configurable piecewise linear FM modulation profiles of up to 8 segments. It supports fine PLL resolution and fast ramp with up to a 200 MHz phase detector rate. The LMX2492/92-Q1 allows any of its registers to be read back. The LMX2492/92-Q1 can operate with a single 3.3 V supply. Moreover, supporting up to 5.25 V charge pump can eliminate the need of external amplifier, leading to a simpler solution with improved phase noise performance.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation datasheet (Rev. B) | PDF | HTML | May 28, 2015 |
| Circuit design | MASH_SEED Optimization and Impact on Spurs (LMX2820) | PDF | HTML | Aug 8, 2024 |
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The LMX2492EVM supports evaluation of the LMX2492 and LMX2492-Q1 which is an ultra-low noise 14 GHz wideband RF PLL with ramp/chirp generation, consisting of a delta-sigma fractional N PLL, phase detector, programmable 5V charge pump and high frequency divider for the VCO. The LMX2492 supports a (...)
X-MWblocks consist of RF and Microwave “Drop-In” components that can be used individually for prototyping or in production assemblies. X-MWblocks are easy to test, integrate, align, and configure to 60 GHz and beyond. No messy Sweat Soldering or Silver Epoxy processes are required. X-MWblocks are (...)
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WQFN (RTW) | 24 | Ultra Librarian |
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