LMK61E0M

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Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

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Product details

Parameters

Features Standard, 7x5mm Output frequency (Max) (MHz) 200 Output level LVCMOS Jitter (ps) 0.5 Stability (ppm) 25 Core supply voltage (V) 3.3 Operating temperature range (C) -40 to 85 open-in-new Find other Oscillators

Package | Pins | Size

QFM (SIA) 8 open-in-new Find other Oscillators

Features

  • Ultra-Low Noise, High Performance
    • Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M
  • LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
  • Default Frequency: 70.656 MHz

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Description

The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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Technical documentation

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Type Title Date
* Datasheet LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet (Rev. A) May 16, 2017
User guides LMK61E2EVM, LMK61E0MEVM User's Guide (Rev. B) Aug. 10, 2017
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
99
Description

The LMK61E0MEVM evaluation modules provides a complete platform to evaluate the jitter performance and configurability of the Texas Instruments LMK61E0M Ultra-Low Jitter Programmable Oscillator with integrated EEPROM and extended frequency margining capabilities.

The LMK61E0MEVM can be used as (...)

Features
  • Ultra low jitter dual output LVCMOS clock generation
  • Powered over USB or externally (SMA connector)
  • Onboard USB to I2C interface
  • Coarse and Fine Frequency margining
  • GUI platform for full access to registers and EEPROM

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
QFM (SIA) 8 View options

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