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Latest version
Version: 1.6.9.1
Release date: 19 Nov 2025
PLLatinum Sim 1.6.9.1 installer binary for Windows operating system
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lock = Requires export approval (1 minute)
Clock buffers
Clock generators
Clock jitter cleaners
Oscillators
RF PLLs & synthesizers
Hardware development
LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization PLLatinum Sim 1.6.9.1 software manifest
PLLatinum Sim 1.6.9.1 is a bugfix release to 1.6.9.
- Fix phase noise trace load initial point scaling up from 0dBc - the initial value should now be correct
- Fix phase noise modeling for devices with VCO post-divider
- Improvements to spur modeling
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Latest version
Version: 1.7.10.1
Release date: 17 Oct 2025
TICS Pro 1.7.10.1 installer binary for Windows operating system
SHA-256 checksum
lock = Requires export approval (1 minute)
Clock generators
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
Hardware development
LMK04208EVM — Two Input, 6+1 Output, Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO LMK04805BEVAL — Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO LMK04806BEVAL — Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK04816BEVAL — Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMK04832SEPEVM — LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter clea LMK04906BEVAL — Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK5B33216EVM — LMK5B33216 evaluation module for 16-output, three DPLL and APLL, network synchronizer with BAW VCO LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2582EVM — LMX2582EVM High Performance, Wideband Frequency PLLatinum RF Synthesizer With Integrated VCO LMX2592EVM — LMX2592EVM high-performance, wideband frequency RF synthesizer PLLATINUM™ integrated circuit LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization LMK04832EVM-CVAL — LMK04832-SP evaluation module for ultra-low-noise, dual-loop, JESD204B clock jitter cleaner LMK04368EPEVM — LMK04368-EP evaluation module for JESD204B/C dual-loop clock jitter cleaner LMK61E0MEVM — LMK61E0M Ultra-Low-Jitter Programmabler Oscillator Evaluation Module LMK61E2EVM — LMK61E2EVM Ultra-Low-Jitter Programmable Oscillator Evaluation Module LMX1204EVM — LMX1204 evaluation module for RF buffer, multiplier and divider with JESD204B/C SYSREF support LMX2594EVM — LMX2594EVM 15-GHz wideband RF synthesizer with phase synchronization & JESD204B evaluation module LMX2595EVM — 20-GHz Wideband RF Synthesizer With Phase Synchronization and JESD204B Evaluation Module LMX2694EPEVM — 15-GHz wideband RF synthesizer evaluation module LMX2572EVM — 6.4-GHz Low Power Wideband RF Synthesizer with Phase Synchronization and JESD204B Support LMX2572LPEVM — 2-GHz Low Power Wideband RF Synthesizer with FSK Modulation Evaluation Module LMX2820EVM — LMX2820 22.6-GHz wideband RF synthesizer evaluation module LMK5B33414EVM — LMK5B33414 evaluation module for 14-output, three DPLL and APLL, network synchronizer with BAW VCO LMK5C33216EVM — LMK5C33216 clock synchronizer DPLL 2 input 16 outputs evaluation module LMK05028EVM — LMK05028 Network Clock Generator and Synchronizer Evaluation Module CDCI6214EVM — CDCI6214 Ultra-Low Power Clock Generator Evaluation Module CDCE6214-Q1EVM — 4 differential and 1 LVCMOS outputs clock generator evaluation module TICS Pro 1.7.10.1 Release Notes
TICS Pro 1.7.10.1 Software Manifest
v1.7.10.1 contains a bugfix for ReadAllRegisters API introduced in v1.7.10.0, and replaces v1.7.10.0.
Devices
Improvements
- See release notes for complete list of updates
- APIs for GetAllRegisters, GetTableData, ImportRegisters, ExportRegisters, and CloseTICSPro added
- ReadAllRegisters API returns values
Bugfixes
- Reading all registers in Simulation/DemoMode no longer overwrites registers with zeros
- ti_ticspro library TICSProOptions.FromFile method fixed
Known Issues
- LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
- Added new APIs: GetAllRegisters, GetTableData, ImportRegisters, ExportRegisters, and CloseTICSPro
- ReadAllRegisters API returns values
- Reading all registers in Simulation/DemoMode no longer overwrites registers with zeros
- ti_ticspro library TICSProOptions.FromFile method fixed
- Added LMK5D33414