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EVALUATION BOARD Download 499
APPLICATION SOFTWARE & FRAMEWORK Download
The LMK04616EVM features LMK04616 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 1200 mW with 16 outputs running, LMK04616 supports 65 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
- Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
- Integrated Loopfilter support easy prototyping
- 1.2 W typical power consumption for 16 outputs at 122.88 MHz
- Jumper configurable supplies with on-board LDOs and DCDC converters
- GUI platform for full access (...)
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW — The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
SIMULATION MODEL Download
- Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
- Export programming configurations for use in end application.
SNAM204.ZIP (126 KB) - IBIS Model SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
DESIGN TOOL Download
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
Clock tree architect programming software
CLOCK-TREE-ARCHITECT — Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
- Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
- Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
- Presents clear and intuitive block (...)