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車載運転支援 SoC

TDA2P-ACD

アクティブ

ADAS 向け、グラフィックス / 画像処理 / ビデオ / ビジョン アクセラレーションの各オプションが利用可能、高性能 SoC ファミリ

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データシート
ユーザー ガイド

TDA2P-ACD

アクティブ
ご注文はこちら

製品詳細

CPU 2 Arm Cortex-A15 Frequency (MHz) 500, 650, 750, 1176, 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image system processor, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A15 Frequency (MHz) 500, 650, 750, 1176, 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators Embedded vision engines, Image system processor, Image video accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (ACD) 784 529 mm² (23 mm × 23 mm) FCBGA (APB) 784 529 mm² (23 mm × 23 mm)
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Vision AccelerationPac
    • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) modules
    • Support for up to eight multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Up to Two Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol with available FD (Flexible Data Rate) functionality
  • MIPI CSI-2 camera serial interface
  • PCI Express® 3.0 port with integrated PHY
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys and OTP data
  • Power, reset, and clock management
  • On-Chip debug With CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-Pin BGA (ACD)
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Vision AccelerationPac
    • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) modules
    • Support for up to eight multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Up to Two Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol with available FD (Flexible Data Rate) functionality
  • MIPI CSI-2 camera serial interface
  • PCI Express® 3.0 port with integrated PHY
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys and OTP data
  • Power, reset, and clock management
  • On-Chip debug With CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-Pin BGA (ACD)

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.
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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート TDA2Px ADAS アプリケーション・プロセッサ、23mm パッケージ（ACD パッケージ）SR1.0 データシート (Rev. F) PDF | HTML 2019/02/05
* ユーザー・ガイド TDA2Px Technical Reference Manual (Rev. C) 2020/02/25
* エラッタ TDA2P、DRA7xxP、AM574x パッケージの製造中止および再設 計 PDF | HTML PDF | HTML 2026/05/29
* エラッタ TDA2Px Silicon Errata (Rev. B) PDF | HTML 2024/09/08
アプリケーション・ノート Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/05/05
アプリケーション・ノート IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/08/24
ホワイト・ペーパー Stereo vision- facing the challenges and seeing the opportunities for ADAS (Rev. A) 2020/07/24
ホワイト・ペーパー Paving the way to self-driving cars with ADAS (Rev. A) 2020/07/24
アプリケーション・ノート AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/01/06
アプリケーション・ノート Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/06/11
アプリケーション・ノート TDA2x/TDA2E Performance (Rev. A) PDF | HTML 2019/06/10
アプリケーション・ノート TDA2Px Performance (Rev. A) 2018/10/22
アプリケーション・ノート The Implementation of YUV422 Output for SRV 2018/08/02
アプリケーション・ノート MMC DLL Tuning (Rev. B) 2018/07/31
アプリケーション・ノート Integrating AUTOSAR on TI SoC: Fundamentals 2018/06/18
アプリケーション・ノート ECC/EDC on TDAxx (Rev. B) 2018/06/13
アプリケーション・ノート Sharing VPE Between VISIONSDK and PSDKLA 2018/05/04
ユーザー・ガイド LP87565C-Q1 and TPS65917-Q1 User’s Guide to Power DRA7xxP and TDA2Pxx (Rev. A) 2018/04/20
アプリケーション・ノート TMS320C66x XMC Memory Protection 2018/01/31
アプリケーション・ノート DSS Bit Exact Output (Rev. A) 2018/01/12
アプリケーション・ノート Flashing Utility - mflash 2018/01/09
アプリケーション・ノート Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/07
アプリケーション・ノート A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/03
アプリケーション・ノート DSS BT656 Workaround for TDA2x (Rev. A) 2017/11/03
機能安全情報 Safety Features on VisionSDK 2017/10/26
アプリケーション・ノート Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/09/12
ホワイト・ペーパー 車載マルチカメラ動作向け次世代アーキテクチャの実現 英語版 2017/07/27
ホワイト・ペーパー Making Cars Safer Through Technology Innovation (Rev. A) 2017/06/07
アプリケーション・ノート Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
アプリケーション・ノート Quad Channel Camera Application for Surround View and CMS Camera Systems (Rev. A) 2016/08/23
アプリケーション・ノート ADAS Power Management 2016/03/07
ホワイト・ペーパー Multicore SoCs stay a step ahead of SoC FPGAs 2016/02/23
ホワイト・ペーパー Surround view camera systems for ADAS (Rev. A) 2015/10/20
アプリケーション・ノート Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/08/13
ホワイト・ペーパー TI Vision SDK, Optimized Vision Libraries for ADAS Systems 2014/04/14
ホワイト・ペーパー TI Gives Sight to Vision-Enabled Automotive Technologies 2013/10/16
ホワイト・ペーパー Empowering Automotive Vision with TI’s Vision AccelerationPac 2013/10/13

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

TDA2PXEVM — TDA2Px 評価基板

TDA2Px EVM は、ADAS アプリケーション開発の迅速化と、開発期間の短縮を実現する評価プラットフォームです。TDA2Px EVM は、TDA2Px システム オン チップ (SoC) をベースとしています。この SoC は、TI の固定 / 浮動小数点デジタル信号プロセッサ (DSP) である TMS320C66x コア、組込みビジョン エンジン (EVE) を搭載した Vision AccelerationPac コア、Arm® Cortex®-A15 MP コア、3D GPU コア、H.264 エンコードとデコードのアクセラレーション機能、デュアル Cortex-M4 (...)
ユーザー ガイド: PDF
購入先：SVTRONICS INC
サポート対象の製品とハードウェア
ソフトウェア開発キット (SDK)

PROCESSOR-SDK-RADAR — レーダー向け RTOS プロセッサ SDK

プロセッサ SDK ビジョン (ビジョン SDK) とプロセッサ SDK レーダー (レーダーSDK) は、TDAx プロセッサ向けのマルチプロセッサ ソフトウェア開発キットです。このソフトウェア フレームワークは、レーダー キャプチャや、レーダー処理、ビデオ キャプチャ、ビデオ前処理、ビデオ分析アルゴリズム、ビデオ ディスプレイが関係する、さまざまな ADAS アプリケーション データ フローの製作を可能にします。。このリリースは、プロセッサ SDK Linux も収録しており、車載 ADAS の機能と、 Linux や GPU を必要とするデモを実現できます。この SDK (...)

サポート対象の製品とハードウェア
ソフトウェア開発キット (SDK)

PROCESSOR-SDK-VISION — ビジョン向け Linux / RTOS プロセッサ SDK

プロセッサ SDK ビジョン (ビジョン SDK) とプロセッサ SDK レーダー (レーダーSDK) は、TDAx プロセッサ向けのマルチプロセッサ ソフトウェア開発キットです。このソフトウェア フレームワークは、レーダー キャプチャや、レーダー処理、ビデオ キャプチャ、ビデオ前処理、ビデオ分析アルゴリズム、ビデオ ディスプレイが関係する、さまざまな ADAS アプリケーション データ フローの製作を可能にします。。このリリースは、プロセッサ SDK Linux も収録しており、車載 ADAS の機能と、 Linux や GPU を必要とするデモを実現できます。この SDK (...)

サポート対象の製品とハードウェア
IDE (統合開発環境)、コンパイラ、またはデバッガ

CCSTUDIO — Code Composer Studio 統合開発環境（IDE）

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

サポート対象の製品とハードウェア
IDE (統合開発環境)、コンパイラ、またはデバッガ

SYSCONFIG — SysConfigのスタンドアロン・デスクトップ・バージョン

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

サポート対象の製品とハードウェア
オペレーティング・システム (OS)

GHS-INTEGRITY-RTOS — Green Hills の INTEGRITY RTOS

Green Hills Software オペレーティング・システムの主力製品、INTEGRITY RTOS はパーティショニング・アーキテクチャを基盤として構築され、トータルな信頼性、絶対的なセキュリティ、および最大リアルタイム・パフォーマンスを実現する組込みシステムを提供しています。INTEGRITY はさまざまな業界での認定実績により、そのリーダーシップを裏付けられており、オペレーティング・システムのリアルタイムな安全性、セキュリティ、信頼性で高いレベルのソリューションを提供しています。

Green Hills Software の詳細については、www.ghs.com (...)
サポート対象の製品とハードウェア
シミュレーション・モデル

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL モデル
サポート対象の製品とハードウェア
シミュレーション・モデル

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS モデル
サポート対象の製品とハードウェア
シミュレーション・モデル

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - しています
サポート対象の製品とハードウェア
計算ツール

CLOCKTREETOOL — Clock Tree Tool for Sitara™ ARM® Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
サポート対象の製品とハードウェア
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCCSP (ACD) 784 Ultra Librarian
FCBGA (APB) 784 Ultra Librarian
TI の評価基板に関する標準契約約款が適用されます。

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