SPRUJD3A July   2025  – October 2025 F28E120SB , F28E120SC

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Power-On Reset (POR)
      4. 3.4.4  Brown-Out-Reset (BOR)
      5. 3.4.5  Watchdog Reset (WDRS)
      6. 3.4.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7  Debugger Reset (SYSRS)
      8. 3.4.8  DCSM Safe Code Copy Reset (SCCRESET)
      9. 3.4.9  Simulate External Reset (SIMRESET.XRS)
      10. 3.4.10 Simulate CPU Reset (SIMRESET_CPU1RS)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection Logic
        2. 3.6.3.2 Flash Uncorrectable ECC Error
        3. 3.6.3.3 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (SYSOSC)
        2. 3.7.1.2 Backup Wide-Range Oscillator (WROSC)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power-Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Dedicated RAM (Mx RAM)
      2. 3.11.2 Global Shared RAM (GSx RAM)
      3. 3.11.3 Access Arbitration
      4. 3.11.4 Memory Error Detection, Correction, and Error Handling
        1. 3.11.4.1 Error Detection and Correction
        2. 3.11.4.2 Error Handling
      5. 3.11.5 Application Test Hooks for Error Detection and Correction
      6. 3.11.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
    15. 3.15 SYSCTRL Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  SYNC_SOC_REGS Registers
      8. 3.15.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.15.9  DEV_CFG_REGS Registers
      10. 3.15.10 CLK_CFG_REGS Registers
      11. 3.15.11 CPU_SYS_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 MEM_CFG_REGS Registers
      14. 3.15.14 MEMORY_ERROR_REGS Registers
      15. 3.15.15 ROM_WAIT_STATE_REGS Registers
      16. 3.15.16 TEST_ERROR_REGS Registers
      17. 3.15.17 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 ECC Logic Self Test
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Open-Drain Configuration Requirements
    10. 8.10 Software
      1. 8.10.1 GPIO Examples
        1. 8.10.1.1 Device GPIO Setup
        2. 8.10.1.2 Device GPIO Toggle
        3. 8.10.1.3 Device GPIO Interrupt
        4. 8.10.1.4 External Interrupt (XINT)
      2. 8.10.2 LED Examples
    11. 8.11 GPIO Registers
      1. 8.11.1 GPIO Base Address Table
      2. 8.11.2 GPIO_CTRL_REGS Registers
      3. 8.11.3 GPIO_DATA_REGS Registers
      4. 8.11.4 GPIO_DATA_READ_REGS Registers
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 MCPWM and GPIO Output X-BAR
      1. 9.2.1 MCPWM X-BAR
        1. 9.2.1.1 MCPWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 PWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Digital Inputs on ADC Pins (AIOs)
    3. 11.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    4. 11.4 Analog Pins and Internal Connections
    5. 11.5 ASBSYS Registers
      1. 11.5.1 ASBSYS Base Address Table
      2. 11.5.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 ADC Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 ADC Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
        1. 12.2.4.1 Expected Conversion Results
        2. 12.2.4.2 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
        1. 12.3.2.1 Trigger Repeaters
          1. 12.3.2.1.1 Oversampling Mode
          2. 12.3.2.1.2 Re-trigger Spread
          3. 12.3.2.1.3 Trigger Repeater Configuration
            1. 12.3.2.1.3.1 Register Shadow Updates
          4. 12.3.2.1.4 Re-Trigger Logic
          5. 12.3.2.1.5 Multi-Path Triggering Behavior
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 Sample Capacitor Reset
      5. 12.3.5 ADC Input Models
      6. 12.3.6 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from MCPWM Trigger
      2. 12.4.2 Multiple Conversions from CPU Timer Trigger
      3. 12.4.3 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  EOC and Interrupt Operation
      1. 12.6.1 Interrupt Overflow
      2. 12.6.2 Continue to Interrupt Mode
      3. 12.6.3 Early Interrupt Configuration Mode
    7. 12.7  Post-Processing Blocks
      1. 12.7.1 PPB Offset Correction
      2. 12.7.2 PPB Error Calculation
      3. 12.7.3 PPB Limit Detection and Zero-Crossing Detection
    8. 12.8  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.8.1 Open Short Detection Implementation
      2. 12.8.2 Detecting an Open Input Pin
      3. 12.8.3 Detecting a Shorted Input Pin
    9. 12.9  Power-Up Sequence
    10. 12.10 ADC Calibration
      1. 12.10.1 ADC Zero Offset Calibration
    11. 12.11 ADC Timings
      1. 12.11.1 ADC Timing Diagrams
      2. 12.11.2 Post-Processing Block Timings
    12. 12.12 Additional Information
      1. 12.12.1 Choosing an Acquisition Window Duration
      2. 12.12.2 Result Register Mapping
      3. 12.12.3 Internal Temperature Sensor
      4. 12.12.4 Designing an External Reference Circuit
      5. 12.12.5 ADC-DAC Loopback Testing
      6. 12.12.6 Internal Test Mode
    13. 12.13 Software
      1. 12.13.1 ADC Examples
        1. 12.13.1.1 ADC Software Triggering
        2. 12.13.1.2 ADC MCPWM Triggering
        3. 12.13.1.3 ADC Temperature Sensor Conversion
        4. 12.13.1.4 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        5. 12.13.1.5 ADC PPB Offset (adc_ppb_offset)
        6. 12.13.1.6 ADC PPB Limits (adc_ppb_limits)
        7. 12.13.1.7 ADC SOC Oversampling
        8. 12.13.1.8 ADC Trigger Repeater Oversampling
    14. 12.14 ADC Registers
      1. 12.14.1 ADC Base Address Table
      2. 12.14.2 ADC_LITE_RESULT_REGS Registers
      3. 12.14.3 ADC_LITE_REGS Registers
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 CMPSS Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Digital Filter
      1. 13.4.1 Filter Initialization Sequence
    5. 13.5 Using the CMPSS
      1. 13.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 13.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.5.3 Calibrating the CMPSS
      4. 13.5.4 Enabling and Disabling the CMPSS Clock
    6. 13.6 CMPSS DAC Output
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
      2. 13.7.2 CMPSS_LITE Examples
        1. 13.7.2.1 CMPSSLITE Asynchronous Trip
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Address Table
      2. 13.8.2 CMPSS_LITE_REGS Registers
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Values
    4. 14.4  Modes of Operation
      1. 14.4.1 Buffer Mode
      2. 14.4.2 Standalone Mode
      3. 14.4.3 Non-inverting Mode
      4. 14.4.4 Subtractor Mode
    5. 14.5  External Filtering
      1. 14.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 14.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 14.6  Error Calibration
      1. 14.6.1 Offset Error
      2. 14.6.2 Gain Error
    7. 14.7  Chopping Feature
    8. 14.8  Enabling and Disabling the PGA Clock
    9. 14.9  Lock Register
    10. 14.10 Analog Front-End Integration
      1. 14.10.1 Analog-to-Digital Converter (ADC)
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 Comparator Subsystem (CMPSS)
      3. 14.10.3 Alternate Functions
    11. 14.11 Examples
      1. 14.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 14.11.2 Buffer Mode
      3. 14.11.3 Low-Side Current Sensing
      4. 14.11.4 Bidirectional Current Sensing
    12. 14.12 Software
      1. 14.12.1 PGA Examples
        1. 14.12.1.1 PGA CMPSSDAC-ADC External Loopback Example
    13. 14.13 PGA Registers
      1. 14.13.1 PGA Base Address Table
      2. 14.13.2 PGA_REGS Registers
  17. 15Multi-Channel Pulse Width Modulator (MCPWM)
    1. 15.1  Introduction
      1. 15.1.1 PWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  MCPWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
        4. 15.4.3.4 MCPWM SYNC Selection
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 15.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 15.4.6 Global Load
        1. 15.4.6.1 One-Shot Load Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-Band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  Trip-Zone (TZ) Submodule
      1. 15.8.1 Purpose of the Trip-Zone Submodule
      2. 15.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.8.2.1 Trip-Zone Configurations
      3. 15.8.3 Generating Trip Event Interrupts
    9. 15.9  Event-Trigger (ET) Submodule
      1. 15.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 15.10 PWM Crossbar (X-BAR)
    11. 15.11 Software
      1. 15.11.1 MCPWM Examples
        1. 15.11.1.1 MCPWM Basic PWM Generation and Updates
        2. 15.11.1.2 MCPWM Basic PWM Generation and Updates
        3. 15.11.1.3 MCPWM Basic PWM generation With DeadBand
        4. 15.11.1.4 MCPWM Basic PWM Generation and Updates without Sysconfig
        5. 15.11.1.5 MCPWM PWM Tripzone Feature Showcase
        6. 15.11.1.6 MCPWM Global Load Feature Showcase
        7. 15.11.1.7 MCPWM DMA Configuration for Dynamic PWM Control
    12. 15.12 MCPWM Registers
      1. 15.12.1 MCPWM Base Address Table
      2. 15.12.2 MCPWM_6CH_REGS Registers
      3. 15.12.3 MCPWM_2CH_REGS Registers
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1 Event Prescaler
      2. 16.5.2 Edge Polarity Select and Qualifier
      3. 16.5.3 Continuous/One-Shot Control
      4. 16.5.4 32-Bit Counter and Phase Control
      5. 16.5.5 CAP1-CAP4 Registers
      6. 16.5.6 eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7 Interrupt Control
      8. 16.5.8 Shadow Load and Lockout Control
      9. 16.5.9 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
    9. 16.9 ECAP Registers
      1. 16.9.1 ECAP Base Address Table
      2. 16.9.2 ECAP_REGS Registers
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  QMA Module
      1. 17.9.1 Modes of Operation
        1. 17.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 17.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 17.9.2 Interrupt and Error Generation
    10. 17.10 eQEP Interrupt Structure
    11. 17.11 Software
      1. 17.11.1 EQEP Examples
        1. 17.11.1.1 Frequency Measurement Using eQEP
        2. 17.11.1.2 Position and Speed Measurement Using eQEP
        3. 17.11.1.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 17.11.1.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 17.12 EQEP Registers
      1. 17.12.1 EQEP Base Address Table
      2. 17.12.2 EQEP_REGS Registers
  20. 18Universal Asynchronous Receiver/Transmitter (UART)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Functional Description
      1. 18.2.1 Transmit and Receive Logic
      2. 18.2.2 Baud-Rate Generation
      3. 18.2.3 Data Transmission
      4. 18.2.4 Serial IR (SIR)
      5. 18.2.5 9-Bit UART Mode
      6. 18.2.6 FIFO Operation
      7. 18.2.7 Interrupts
      8. 18.2.8 Loopback Operation
      9. 18.2.9 DMA Operation
        1. 18.2.9.1 Receiving Data Using UART with DMA
        2. 18.2.9.2 Transmitting Data Using UART with DMA
    3. 18.3 Initialization and Configuration
    4. 18.4 Software
      1. 18.4.1 UART Examples
        1. 18.4.1.1 UART Echoback
        2. 18.4.1.2 UART Loopback
        3. 18.4.1.3 UART Loopback with interrupt
        4. 18.4.1.4 UART Digital Loopback with DMA
    5. 18.5 UART Registers
      1. 18.5.1 UART Base Address Table
      2. 18.5.2 UART_REGS Registers
      3. 18.5.3 UART_REGS_WRITE Registers
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
      4. 19.2.4 DMA Support
    3. 19.3 SPI Operation
      1. 19.3.1  Introduction to Operation
      2. 19.3.2  Controller Mode
      3. 19.3.3  Peripheral Mode
      4. 19.3.4  Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5  Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6  SPI Clocking Schemes
      7. 19.3.7  SPI FIFO Description
      8. 19.3.8  SPI DMA Transfers
        1. 19.3.8.1 Transmitting Data Using SPI with DMA
        2. 19.3.8.2 Receiving Data Using SPI with DMA
      9. 19.3.9  SPI High-Speed Mode
      10. 19.3.10 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Controller Mode Transmit
        2.       679
          1. 19.4.5.2.1 3-Wire Controller Mode Receive
        3.       681
          1. 19.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       683
          1. 19.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI Digital Loopback with DMA
        4. 19.5.1.4 SPI EEPROM
        5. 19.5.1.5 SPI DMA EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Controller Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Clock Stretching
      10. 20.3.10 Arbitration
      11. 20.3.11 Digital Loopback Mode
      12. 20.3.12 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Registers to Driverlib Functions
      2. 20.6.2 I2C Examples
        1. 20.6.2.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.2.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.2.3 I2C Digital Loopback with FIFO Interrupts
        4. 20.6.2.4 I2C EEPROM
        5. 20.6.2.5 I2C EEPROM
        6. 20.6.2.6 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Address Table
      2. 20.7.2 I2C_REGS Registers
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
  24. 22Revision History

18.5.2 UART_REGS Registers

Table 18-2 lists the memory-mapped registers for the UART_REGS registers. All register offset addresses not listed in Table 18-2 should be considered as reserved locations and the register contents should not be modified.

Table 18-2 UART_REGS Registers
OffsetAcronymRegister NameWrite Protection
0hUARTDRUART Data
2hUARTRSRUART Receive Status/Error Clear
ChUARTFRUART Flag
10hUARTILPRUART IrDA Low-Power Register
12hUARTIBRDUART Integer Baud-Rate Divisor
14hUARTFBRDUART Fractional Baud-Rate Divisor
16hUARTLCRHUART Line Control
18hUARTCTLUART Control
1AhUARTIFLSUART Interrupt FIFO Level Select
1ChUARTIMUART Interrupt Mask
1EhUARTRISUART Raw Interrupt Status
20hUARTMISUART Masked Interrupt Status
22hUARTICRUART Interrupt Clear
24hUARTDMACTLUART DMA Control
40hUART_GLB_INT_ENUART Global Interrupt Enable Register
42hUART_GLB_INT_FLGUART Global Interrupt Flag Register
44hUART_GLB_INT_CLRUART Global Interrupt Clear Register
52hUART9BITADDRUART 9-Bit Self Address
54hUART9BITAMASKUART 9-Bit Self Address Mask
7E0hUARTPPUART Peripheral Properties
7E8hUARTPeriphID4UART Peripheral Identification 4
7EAhUARTPeriphID5UART Peripheral Identification 5
7EChUARTPeriphID6UART Peripheral Identification 6
7EEhUARTPeriphID7UART Peripheral Identification 7
7F0hUARTPeriphID0UART Peripheral Identification 0
7F2hUARTPeriphID1UART Peripheral Identification 1
7F4hUARTPeriphID2UART Peripheral Identification 2
7F6hUARTPeriphID3UART Peripheral Identification 3
7F8hUARTPCellID0UART PrimeCell Identification 0
7FAhUARTPCellID1UART PrimeCell Identification 1
7FChUARTPCellID2UART PrimeCell Identification 2
7FEhUARTPCellID3UART PrimeCell Identification 3

Complex bit access types are encoded to fit into small table cells. Table 18-3 shows the codes that are used for access types in this section.

Table 18-3 UART_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

18.5.2.1 UARTDR Register (Offset = 0h) [Reset = 00000000h]

UARTDR is shown in Figure 18-4 and described in Table 18-4.

Return to the Summary Table.

IMPORTANT: This register is read sensitive. This register is the data register (the interface to the FIFOs).
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of
the transmit FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.

Figure 18-4 UARTDR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDOEBEPEFEDATA
R-0hR-0hR-0hR-0hR-0hR/W-0h
Table 18-4 UARTDR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11OER0hUART Overrun Error

0 No data has been lost due to a FIFO overrun.
1 New data was received when the FIFO was full, resulting in data loss.

Reset type: PER.RESET

10BER0hUART Break Error

0 No break condition has occurred
1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received.

Reset type: PER.RESET

9PER0hUART Parity Error

0 No parity error has occurred
1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of the FIFO.

Reset type: PER.RESET

8FER0hUART Framing Error

0 No framing error has occurred
1 The received character does not have a valid stop bit (a valid stop bit is 1).

Reset type: PER.RESET

7-0DATAR/W0hData Transmitted or Received
Data that is to be transmitted via the UART is written to this field.
When read, this field contains the data that was received by the UART.

For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.

Reset type: PER.RESET

18.5.2.2 UARTRSR Register (Offset = 2h) [Reset = 00000000h]

UARTRSR is shown in Figure 18-5 and described in Table 18-5.

Return to the Summary Table.

The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared on reset.

Figure 18-5 UARTRSR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDOEBEPEFE
R-0hR-0hR-0hR-0hR-0h
Table 18-5 UARTRSR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3OER0hUART Overrun Error

0 No data has been lost due to a FIFO overrun.
1 New data was received when the FIFO was full, resulting in data loss.
This bit is cleared by a write to UARTECR.The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.

Reset type: PER.RESET

2BER0hUART Break Error

0 No break condition has occurred
1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

Reset type: PER.RESET

1PER0hUART Parity Error

0 No parity error has occurred
1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.

Reset type: PER.RESET

0FER0hUART Framing Error
0 No framing error has occurred
1 The received character does not have a valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO.

Reset type: PER.RESET

18.5.2.3 UARTFR Register (Offset = Ch) [Reset = 00000090h]

UARTFR is shown in Figure 18-6 and described in Table 18-6.

Return to the Summary Table.

The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.

Figure 18-6 UARTFR Register
3130292827262524
RESERVEDTXFIFOLVL
R-0hR-0h
2322212019181716
RESERVEDRXFIFOLVL
R-0hR-0h
15141312111098
RESERVEDRESERVED
R-0hR-0h
76543210
TXFERXFFTXFFRXFEBUSYRESERVEDRESERVEDRESERVED
R-1hR-0hR-0hR-1hR-0hR-0hR-0hR-0h
Table 18-6 UARTFR Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24TXFIFOLVLR0hUART Transmit FIFO Level
Indicates number of untransmitted TX FIFO entries (intended for CCS debugs)

Reset type: PER.RESET

23-21RESERVEDR0hReserved
20-16RXFIFOLVLR0hUART Receive FIFO Level
Indicates number of unread RX FIFO entries (intended for CCS debugs)

Reset type: PER.RESET

15-9RESERVEDR0hReserved
8RESERVEDR0hReserved
7TXFER1hUART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.

0 The transmitter has data to transmit.
1 If the FIFO is disabled (FEN is 0), the transmit holding register is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.

Reset type: PER.RESET

6RXFFR0hUART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.

0 The receiver can receive data.
1 If the FIFO is disabled (FEN is 0), the receive holding register is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.

Reset type: PER.RESET

5TXFFR0hUART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.

0 The transmitter is not full.
1 If the FIFO is disabled (FEN is 0), the transmit holding register is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.

Reset type: PER.RESET

4RXFER1hUART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.

0 The receiver is not empty.
1 If the FIFO is disabled (FEN is 0), the receive holding register is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.

Reset type: PER.RESET

3BUSYR0hUART Busy

0 The UART is not busy.
1 The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled).

Reset type: PER.RESET

2RESERVEDR0hReserved
1RESERVEDR0hReserved
0RESERVEDR0hReserved

18.5.2.4 UARTILPR Register (Offset = 10h) [Reset = 00000000h]

UARTILPR is shown in Figure 18-7 and described in Table 18-7.

Return to the Summary Table.

The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock.

Figure 18-7 UARTILPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDILPDVSR
R-0hR/W-0h
Table 18-7 UARTILPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0ILPDVSRR/W0hIrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
Because the IrLPBaud16 clock is used to sample transmitted data irrespective of mode, the
ILPDVSR field must be programmed in both low power and normal mode,such that FIrLPBaud16 is between 1.42 and 2.12 MHz, resulting in a low-power pulse duration of 1.41-2.11 us (three times the
period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but pulses greater than 1.4 us are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated

Reset type: PER.RESET

18.5.2.5 UARTIBRD Register (Offset = 12h) [Reset = 00000000h]

UARTIBRD is shown in Figure 18-8 and described in Table 18-8.

Return to the Summary Table.

The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register.

Figure 18-8 UARTIBRD Register
313029282726252423222120191817161514131211109876543210
RESERVEDDIVINT
R-0hR/W-0h
Table 18-8 UARTIBRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DIVINTR/W0hInteger Baud-Rate Divisor
The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register.

Reset type: PER.RESET

18.5.2.6 UARTFBRD Register (Offset = 14h) [Reset = 00000000h]

UARTFBRD is shown in Figure 18-9 and described in Table 18-9.

Return to the Summary Table.

The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See 'Baud-Rate Generation' on page 1165
for configuration details.

Figure 18-9 UARTFBRD Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDDIVFRAC
R-0hR/W-0h
Table 18-9 UARTFBRD Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0DIVFRACR/W0hFractional Baud-Rate Divisor
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register.

Reset type: PER.RESET

18.5.2.7 UARTLCRH Register (Offset = 16h) [Reset = 00000000h]

UARTLCRH is shown in Figure 18-10 and described in Table 18-10.

Return to the Summary Table.

The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.

Figure 18-10 UARTLCRH Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
SPSWLENFENSTP2EPSPENBRK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-10 UARTLCRH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7SPSR/W0hUART Stick Parity Select
UART Stick Parity Select
0 Stick parity is disabled (default)
1 Stick parity is enabled. When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1.

Reset type: PER.RESET

6-5WLENR/W0hUART Word Length
The bits indicate the number of data bits transmitted or received in a frame as follows:

0x0 5 bits (default)
0x1 6 bits
0x2 7 bits
0x3 8 bits

Reset type: PER.RESET

4FENR/W0hUART Enable FIFOs

0 The FIFOs are disabled. The FIFOs become 1-byte-deep holding registers.
1 The transmit and receive FIFO buffers are enabled (FIFO mode).

Reset type: PER.RESET

3STP2R/W0hUART Two Stop Bits Select

0 One stop bit is transmitted at the end of a frame.
1 Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received.

Reset type: PER.RESET

2EPSR/W0hUART Even Parity Select

0 Odd parity is performed, which checks for an odd number of 1s.
1 Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits.
This bit has no effect when parity is disabled by the PEN bit.

Reset type: PER.RESET

1PENR/W0hUART Parity Enable

0 Parity is disabled and no parity bit is added to the data frame.
1 Parity checking and generation is enabled.

Reset type: PER.RESET

0BRKR/W0hUART Send Break

0 Normal use.
1 A Low level is continually output on the UnTx signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods).

Reset type: PER.RESET

18.5.2.8 UARTCTL Register (Offset = 18h) [Reset = 00000300h]

UARTCTL is shown in Figure 18-11 and described in Table 18-11.

Return to the Summary Table.

The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.

Figure 18-11 UARTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRXETXE
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-1h
76543210
LBERESERVEDHSEEOTRESERVEDSIRLPSIRENUARTEN
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-11 UARTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13-12RESERVEDR0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RXER/W1hUART Receive Enable

0 The receive section of the UART is disabled.
1 The receive section of the UART is enabled.
If the UART is disabled in the middle of a receive, it completes the current character before stopping.To enable reception, the UARTEN bit must also be set.

Reset type: PER.RESET

8TXER/W1hUART Transmit Enable

0 The transmit section of the UART is disabled.
1 The transmit section of the UART is enabled.
If the UART is disabled in the middle of a transmission, it completes the current character before stopping. To enable transmission, the UARTEN bit must also be set.

Reset type: PER.RESET

7LBER/W0hUART Loop Back Enable

0 Normal operation.
1 The UnTx path is fed through the UnRx path.

Reset type: PER.RESET

6RESERVEDR0hReserved
5HSER/W0hHigh-Speed Enable

0 The UART is clocked using the system clock divided by 16.
1 The UART is clocked using the system clock divided by 8.

Reset type: PER.RESET

4EOTR/W0hEnd of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS register.

0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met.
1 The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer.

Reset type: PER.RESET

3RESERVEDR/W0hReserved
2SIRLPR/W0hUART SIR Low-Power Mode
This bit selects the IrDA encoding mode.

0 Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period.
1 The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate.
Setting this bit uses less power, but might reduce transmission distances.

Reset type: PER.RESET

1SIRENR/W0hUART SIR Enable

0 Normal operation.
1 The IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol.

Reset type: PER.RESET

0UARTENR/W0hUART Enable

0 The UART is disabled.
1 The UART is enabled.
If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

Reset type: PER.RESET

18.5.2.9 UARTIFLS Register (Offset = 1Ah) [Reset = 00000012h]

UARTIFLS is shown in Figure 18-12 and described in Table 18-12.

Return to the Summary Table.

The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character.
Therefore, changing the trigger level does not trigger an interrupt using the new level until another character is received.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 18-12 UARTIFLS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRXIFLSEL_FINE
R-0hR/W-0h
15141312111098
RESERVEDTXIFLSEL_FINE
R-0hR/W-0h
76543210
RESERVEDRXIFLSELTXIFLSEL
R-0hR/W-2hR/W-2h
Table 18-12 UARTIFLS Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16RXIFLSEL_FINER/W0hValue Description
0x0 RX FIFO FULL - 16 filled spots
0x1 RX FIFO greater than or equal to 1/16 full - at least 1 filled spots
0x2 RX FIFO greater than or equal to 2/16 full - at least 2 filled spots
...
0xE RX FIFO greater than or equal to 14/16 full - at least 14 filled spots
0xF RX FIFO greater than or equal to 15/16 full - at least 15 filled spots

Note : This field is considered only if RXIFLSEL = 0x5

Reset type: PER.RESET

15-12RESERVEDR0hReserved
11-8TXIFLSEL_FINER/W0hValue Description
0x0 TX FIFO empty - 16 empty slots
0x1 TX FIFO less than or equal to 1/16 full - atleast 15 empty slots
0x2 TX FIFO less than or equal to 2/16 full - atleast 14 empty slots
...
0xE TX FIFO less than or equal to 14/16 full - atleast 2 empty slots
0xF TX FIFO less than or equal to 15/16 full - atleast 1 empty slots

Note : This field is considered only if TXIFLSEL = 0x5

Reset type: PER.RESET

7-6RESERVEDR0hReserved
5-3RXIFLSELR/W2hThe trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO greater than or equal to 1/8 full - at least 2 filled spots
0x1 RX FIFO greater than or equal to 1/4 full - at least 4 filled spots
0x2 RX FIFO greater than or equal to 1/2 full - at least 8 filled spots (default)
0x3 RX FIFO greater than or equal to 3/4 full - at least 12 filled spots
0x4 RX FIFO greater than or equal to 7/8 full - at least 14 filled spots
0x5 Fine-grained RX FIFO Mode (Refer to RXIFLSEL_FINE field of this register)
0x6-0x7 Reserved

Reset type: PER.RESET

2-0TXIFLSELR/W2hThe trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO less than or equal to 1/8 full - at least 14 empty spots
0x1 TX FIFO less than or equal to 1/4 full - at least 12 empty spots
0x2 TX FIFO less than or equal to 1/2 full - at least 8 empty spots (default)
0x3 TX FIFO less than or equal to 3/4 full - at least 4 empty spots
0x4 TX FIFO less than or equal to 7/8 full - at least 2 empty spots
0x5 Fine-grained TX FIFO Mode (Refer to TXIFLSEL_FINE field of this register)
0x6-0x7 Reserved

Note: If the EOT bit in UARTCTL is set, the transmit
interrupt is generated once the FIFO is completely empty and
all data including stop bits have left the transmit serializer. In
this case, the setting of TXIFLSEL is ignored.

Reset type: PER.RESET

18.5.2.10 UARTIM Register (Offset = 1Ch) [Reset = 00000000h]

UARTIM is shown in Figure 18-13 and described in Table 18-13.

Return to the Summary Table.

The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.

Figure 18-13 UARTIM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXIMDMARXIM
R-0hR/W-0hR/W-0h
15141312111098
RESERVED9BITIMRESERVEDOEIMBEIMPEIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
FEIMRTIMTXIMRXIMRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 18-13 UARTIM Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17DMATXIMR/W0hTransmit DMA Interrupt Mask

0 The DMATXRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the DMATXRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

16DMARXIMR/W0hReceive DMA Interrupt Mask

0 The DMARXRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the DMARXRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

15-13RESERVEDR0hReserved
129BITIMR/W0h9-Bit Mode Interrupt Mask

0 The 9BITRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

11RESERVEDR/W0hReserved
10OEIMR/W0hUART Overrun Error Interrupt Mask

0 The OERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set.

Reset type: PER.RESET

9BEIMR/W0hUART Break Error Interrupt Mask

0 The BERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set.

Reset type: PER.RESET

8PEIMR/W0hUART Parity Error Interrupt Mask

0 The PERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set.

Reset type: PER.RESET

7FEIMR/W0hUART Framing Error Interrupt Mask

0 The FERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set.

Reset type: PER.RESET

6RTIMR/W0hUART Receive Time-Out Interrupt Mask

0 The RTRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

5TXIMR/W0hUART Transmit Interrupt Mask

0 The TXRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

4RXIMR/W0hUART Receive Interrupt Mask

0 The RXRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set.

Reset type: PER.RESET

3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

18.5.2.11 UARTRIS Register (Offset = 1Eh) [Reset = 00000000h]

UARTRIS is shown in Figure 18-14 and described in Table 18-14.

Return to the Summary Table.

The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.

Figure 18-14 UARTRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXRISDMARXRIS
R-0hR-0hR-0h
15141312111098
RESERVED9BITRISRESERVEDOERISBERISPERIS
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
FERISRTRISTXRISRXRISRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 18-14 UARTRIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17DMATXRISR0hTransmit DMA Raw Interrupt Status

0 No interrupt
1 The transmit DMA has completed.
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.

Reset type: PER.RESET

16DMARXRISR0hReceive DMA Raw Interrupt Status

0 No interrupt
1 The receive DMA has completed.
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.

Reset type: PER.RESET

15-13RESERVEDR0hReserved
129BITRISR0h9-Bit Mode Raw Interrupt Status

0 No interrupt
1 A receive address match has occurred.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register.

Reset type: PER.RESET

11RESERVEDR0hReserved
10OERISR0hUART Overrun Error Raw Interrupt Status

0 No interrupt
1 An overrun error has occurred.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.

Reset type: PER.RESET

9BERISR0hUART Break Error Raw Interrupt Status

0 No interrupt
1 A break error has occurred.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.

Reset type: PER.RESET

8PERISR0hUART Parity Error Raw Interrupt Status

0 No interrupt
1 A parity error has occurred.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.

Reset type: PER.RESET

7FERISR0hUART Framing Error Raw Interrupt Status

0 No interrupt
1 A framing error has occurred.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.

Reset type: PER.RESET

6RTRISR0hUART Receive Time-Out Raw Interrupt Status

0 No interrupt
1 A receive time out has occurred.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.

Reset type: PER.RESET

5TXRISR0hUART Transmit Raw Interrupt Status

0 No interrupt
1 If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register.If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.

Reset type: PER.RESET

4RXRISR0hUART Receive Raw Interrupt Status

0 No interrupt
1 The receive FIFO level has passed through the condition defined in the UARTIFLS register.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.

Reset type: PER.RESET

3RESERVEDR0hReserved
2RESERVEDR0hReserved
1RESERVEDR0hReserved
0RESERVEDR0hReserved

18.5.2.12 UARTMIS Register (Offset = 20h) [Reset = 00000000h]

UARTMIS is shown in Figure 18-15 and described in Table 18-15.

Return to the Summary Table.

The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.

Figure 18-15 UARTMIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXMISDMARXMIS
R-0hR-0hR-0h
15141312111098
RESERVED9BITMISRESERVEDOEMISBEMISPEMIS
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
FEMISRTMISTXMISRXMISRESERVEDRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 18-15 UARTMIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17DMATXMISR0hTransmit DMA Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to the completion of the transmit DMA.
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.

Reset type: PER.RESET

16DMARXMISR0hReceive DMA Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to the completion of the receive DMA.
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.

Reset type: PER.RESET

15-13RESERVEDR0hReserved
129BITMISR0h9-Bit Mode Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a receive address match.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register.

Reset type: PER.RESET

11RESERVEDR0hReserved
10OEMISR0hUART Overrun Error Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an overrun error.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.

Reset type: PER.RESET

9BEMISR0hUART Break Error Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a break error.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.

Reset type: PER.RESET

8PEMISR0hUART Parity Error Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a parity error.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.

Reset type: PER.RESET

7FEMISR0hUART Framing Error Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a framing error.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.

Reset type: PER.RESET

6RTMISR0hUART Receive Time-Out Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a receive time out.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.

Reset type: PER.RESET

5TXMISR0hUART Transmit Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set).
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.

Reset type: PER.RESET

4RXMISR0hUART Receive Masked Interrupt Status

0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to passing through the specified receive FIFO level.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.

Reset type: PER.RESET

3RESERVEDR0hReserved
2RESERVEDR0hReserved
1RESERVEDR0hReserved
0RESERVEDR0hReserved

18.5.2.13 UARTICR Register (Offset = 22h) [Reset = 00000000h]

UARTICR is shown in Figure 18-16 and described in Table 18-16.

Return to the Summary Table.

The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.

Figure 18-16 UARTICR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXICDMARXIC
R-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVED9BITICEOTICOEICBEICPEIC
R-0hR/W-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
FEICRTICTXICRXICRESERVEDRESERVEDRESERVEDRESERVED
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 18-16 UARTICR Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17DMATXICR-0/W1S0hTransmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the UARTRIS register and the DMATXMIS bit in the UARTMIS register.

Reset type: PER.RESET

16DMARXICR-0/W1S0hReceive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the UARTRIS register and the DMARXMIS bit in the UARTMIS register.

Reset type: PER.RESET

15-13RESERVEDR0hReserved
129BITICR/W0h9-Bit Mode Interrupt Clear
Writing a 1 to this bit clears the 9BITRIS bit in the UARTRIS register and the 9BITMIS bit in the UARTMIS register.

Reset type: PER.RESET

11EOTICR-0/W1S0hEnd of Transmission Interrupt Clear
Writing a 1 to this bit clears the EOTRIS bit in the UARTRIS register and the EOTMIS bit in the UARTMIS register.

Reset type: PER.RESET

10OEICR-0/W1S0hOverrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the UARTMIS register.

Reset type: PER.RESET

9BEICR-0/W1S0hBreak Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register.

Reset type: PER.RESET

8PEICR-0/W1S0hParity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register.

Reset type: PER.RESET

7FEICR-0/W1S0hFraming Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the UARTMIS register.

Reset type: PER.RESET

6RTICR-0/W1S0hReceive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register.

Reset type: PER.RESET

5TXICR-0/W1S0hTransmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and the TXMIS bit in the UARTMIS register.

Reset type: PER.RESET

4RXICR-0/W1S0hReceive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register.

Reset type: PER.RESET

3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1RESERVEDR-0/W1S0hReserved
0RESERVEDR-0/W1S0hReserved

18.5.2.14 UARTDMACTL Register (Offset = 24h) [Reset = 00000000h]

UARTDMACTL is shown in Figure 18-17 and described in Table 18-17.

Return to the Summary Table.

UART DMA Control

Figure 18-17 UARTDMACTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMAERRTXDMAERXDMAE
R-0hR/W-0hR/W-0hR/W-0h
Table 18-17 UARTDMACTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2DMAERRR/W0hDMA on Error

0 DMA receive requests are unaffected when a receive error occurs.
1 DMA receive requests are automatically disabled when a receive error occurs.

Reset type: PER.RESET

1TXDMAER/W0hTransmit DMA Enable

0 DMA for the transmit FIFO is disabled.
1 DMA for the transmit FIFO is enabled.

Reset type: PER.RESET

0RXDMAER/W0hReceive DMA Enable

0 DMA for the receive FIFO is disabled.
1 DMA for the receive FIFO is enabled.

Reset type: PER.RESET

18.5.2.15 UART_GLB_INT_EN Register (Offset = 40h) [Reset = 00000000h]

UART_GLB_INT_EN is shown in Figure 18-18 and described in Table 18-18.

Return to the Summary Table.

The UART_GLB_INT_EN register is used to enable interrupt from UART to PIE

Figure 18-18 UART_GLB_INT_EN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVED
R-0hR/W-0h
Table 18-18 UART_GLB_INT_EN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RESERVEDR/W0hReserved

18.5.2.16 UART_GLB_INT_FLG Register (Offset = 42h) [Reset = 00000000h]

UART_GLB_INT_FLG is shown in Figure 18-19 and described in Table 18-19.

Return to the Summary Table.

The UART_GLB_INT_FLG register contains the current status of the UART interrupt

Figure 18-19 UART_GLB_INT_FLG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT_FLG
R-0hR-0h
Table 18-19 UART_GLB_INT_FLG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0INT_FLGR0hGlobal Interrupt Flag for UART INT.
This bit determines whether the SINTREQUEST is generated by UART
This bit can be cleared by writing a 1 to the corresponding bit in the UART_GLB_INT_CLR register.

Reset type: SYSRSn

18.5.2.17 UART_GLB_INT_CLR Register (Offset = 44h) [Reset = 00000000h]

UART_GLB_INT_CLR is shown in Figure 18-20 and described in Table 18-20.

Return to the Summary Table.

The UART_GLB_INT_CLR register is used to clear the interrupt flags in UART_GLB_INT_FLG register.

Figure 18-20 UART_GLB_INT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT_FLG_CLR
R-0hR/W1C-0h
Table 18-20 UART_GLB_INT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0INT_FLG_CLRR/W1C0hGlobal Interrupt flag clear for UART INT.
This bit is used to clear the corresponding bit in the UART_GLB_INT_FLG register. Write 1 to clear the INT_FLG bit. Writing 0 has no effect.

Reset type: SYSRSn

18.5.2.18 UART9BITADDR Register (Offset = 52h) [Reset = 00000000h]

UART9BITADDR is shown in Figure 18-21 and described in Table 18-21.

Return to the Summary Table.

The UART9BITADDR register is used to write the specific address that should be matched with the
receiving byte when the 9-bit Address Mask (UART9BITAMASK) is set to 0xFF. This register is
used in conjunction with UART9BITAMASK to form a match for address-byte received.

Figure 18-21 UART9BITADDR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
9BITENRESERVED
R/W-0hR-0h
76543210
ADDR
R/W-0h
Table 18-21 UART9BITADDR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
159BITENR/W0hEnable 9-Bit Mode

0 9-bit mode is disabled.
1 9-bit mode is enabled.

Reset type: PER.RESET

14-8RESERVEDR0hReserved
7-0ADDRR/W0hSelf Address for 9-Bit Mode
This field contains the address that should be matched when UART9BITAMASK is 0xFF.

Reset type: PER.RESET

18.5.2.19 UART9BITAMASK Register (Offset = 54h) [Reset = 000000FFh]

UART9BITAMASK is shown in Figure 18-22 and described in Table 18-22.

Return to the Summary Table.

The UART9BITAMASK register is used to enable the address mask for 9-bit mode. The address
bits are masked to create a set of addresses to be matched with the received address byte.

Figure 18-22 UART9BITAMASK Register
313029282726252423222120191817161514131211109876543210
RESERVEDMASK
R-0hR/W-FFh
Table 18-22 UART9BITAMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0MASKR/WFFhSelf Address Mask for 9-Bit Mode
This field contains the address mask that creates a set of addresses that should be matched.

Reset type: PER.RESET

18.5.2.20 UARTPP Register (Offset = 7E0h) [Reset = 00000002h]

UARTPP is shown in Figure 18-23 and described in Table 18-23.

Return to the Summary Table.

The UARTPP register provides information regarding the properties of the UART module.

Figure 18-23 UARTPP Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDMSEMSNBSC
R-0hR-0hR-0hR-1hR-0h
Table 18-23 UARTPP Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3MSER0hModem Support Extended

0 The UART module does not provide extended support for modem control.
1 The UART module provides extended support for modem control including UARTnDTR, UARTnDSR, UARTnDCD, and UARTnRI.

Reset type: PER.RESET

2MSR0hModem Support

0 The UART module does not provide support for modem control.
1 The UART module provides support for modem control including UARTnRTS and UARTnCTS.

Reset type: PER.RESET

1NBR1h9-Bit Support

0 The UART module does not provide support for the transmission of 9-bit data for RS-485 support.
1 The UART module provides support for the transmission of 9-bit data for RS-485 support.

Reset type: PER.RESET

0SCR0hSmart Card Support

0 The UART module does not provide smart card support.
1 The UART module provides smart card support.

Reset type: PER.RESET

18.5.2.21 UARTPeriphID4 Register (Offset = 7E8h) [Reset = 00000060h]

UARTPeriphID4 is shown in Figure 18-24 and described in Table 18-24.

Return to the Summary Table.

UART Peripheral Identification 4

Figure 18-24 UARTPeriphID4 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID4
R-0hR-60h
Table 18-24 UARTPeriphID4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID4R60hUART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.22 UARTPeriphID5 Register (Offset = 7EAh) [Reset = 00000000h]

UARTPeriphID5 is shown in Figure 18-25 and described in Table 18-25.

Return to the Summary Table.

UART Peripheral Identification 5

Figure 18-25 UARTPeriphID5 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID5
R-0hR-0h
Table 18-25 UARTPeriphID5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID5R0hUART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.23 UARTPeriphID6 Register (Offset = 7ECh) [Reset = 00000000h]

UARTPeriphID6 is shown in Figure 18-26 and described in Table 18-26.

Return to the Summary Table.

UART Peripheral Identification 6

Figure 18-26 UARTPeriphID6 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID6
R-0hR-0h
Table 18-26 UARTPeriphID6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID6R0hUART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.24 UARTPeriphID7 Register (Offset = 7EEh) [Reset = 00000000h]

UARTPeriphID7 is shown in Figure 18-27 and described in Table 18-27.

Return to the Summary Table.

UART Peripheral Identification 7

Figure 18-27 UARTPeriphID7 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID7
R-0hR-0h
Table 18-27 UARTPeriphID7 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID7R0hUART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.25 UARTPeriphID0 Register (Offset = 7F0h) [Reset = 00000011h]

UARTPeriphID0 is shown in Figure 18-28 and described in Table 18-28.

Return to the Summary Table.

UART Peripheral Identification 0

Figure 18-28 UARTPeriphID0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID0
R-0hR-11h
Table 18-28 UARTPeriphID0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID0R11hUART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.26 UARTPeriphID1 Register (Offset = 7F2h) [Reset = 00000000h]

UARTPeriphID1 is shown in Figure 18-29 and described in Table 18-29.

Return to the Summary Table.

UART Peripheral Identification 1

Figure 18-29 UARTPeriphID1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID1
R-0hR-0h
Table 18-29 UARTPeriphID1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID1R0hUART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.27 UARTPeriphID2 Register (Offset = 7F4h) [Reset = 00000018h]

UARTPeriphID2 is shown in Figure 18-30 and described in Table 18-30.

Return to the Summary Table.

UART Peripheral Identification 2

Figure 18-30 UARTPeriphID2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID2
R-0hR-18h
Table 18-30 UARTPeriphID2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID2R18hUART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.28 UARTPeriphID3 Register (Offset = 7F6h) [Reset = 00000001h]

UARTPeriphID3 is shown in Figure 18-31 and described in Table 18-31.

Return to the Summary Table.

UART Peripheral Identification 3

Figure 18-31 UARTPeriphID3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPID3
R-0hR-1h
Table 18-31 UARTPeriphID3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0PID3R1hUART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.

Reset type: PER.RESET

18.5.2.29 UARTPCellID0 Register (Offset = 7F8h) [Reset = 0000000Dh]

UARTPCellID0 is shown in Figure 18-32 and described in Table 18-32.

Return to the Summary Table.

UART PrimeCell Identification 0

Figure 18-32 UARTPCellID0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDCID0
R-0hR-Dh
Table 18-32 UARTPCellID0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CID0RDhUART PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.

Reset type: PER.RESET

18.5.2.30 UARTPCellID1 Register (Offset = 7FAh) [Reset = 000000F0h]

UARTPCellID1 is shown in Figure 18-33 and described in Table 18-33.

Return to the Summary Table.

UART PrimeCell Identification 1

Figure 18-33 UARTPCellID1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDCID1
R-0hR-F0h
Table 18-33 UARTPCellID1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CID1RF0hUART PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.

Reset type: PER.RESET

18.5.2.31 UARTPCellID2 Register (Offset = 7FCh) [Reset = 00000005h]

UARTPCellID2 is shown in Figure 18-34 and described in Table 18-34.

Return to the Summary Table.

UART PrimeCell Identification 2

Figure 18-34 UARTPCellID2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDCID2
R-0hR-5h
Table 18-34 UARTPCellID2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CID2R5hUART PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.

Reset type: PER.RESET

18.5.2.32 UARTPCellID3 Register (Offset = 7FEh) [Reset = 000000B1h]

UARTPCellID3 is shown in Figure 18-35 and described in Table 18-35.

Return to the Summary Table.

UART PrimeCell Identification 3

Figure 18-35 UARTPCellID3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDCID3
R-0hR-B1h
Table 18-35 UARTPCellID3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0CID3RB1hUART PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.

Reset type: PER.RESET