SPRUJD3A July   2025  – October 2025 F28E120SB , F28E120SC

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Power-On Reset (POR)
      4. 3.4.4  Brown-Out-Reset (BOR)
      5. 3.4.5  Watchdog Reset (WDRS)
      6. 3.4.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7  Debugger Reset (SYSRS)
      8. 3.4.8  DCSM Safe Code Copy Reset (SCCRESET)
      9. 3.4.9  Simulate External Reset (SIMRESET.XRS)
      10. 3.4.10 Simulate CPU Reset (SIMRESET_CPU1RS)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection Logic
        2. 3.6.3.2 Flash Uncorrectable ECC Error
        3. 3.6.3.3 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (SYSOSC)
        2. 3.7.1.2 Backup Wide-Range Oscillator (WROSC)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power-Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Dedicated RAM (Mx RAM)
      2. 3.11.2 Global Shared RAM (GSx RAM)
      3. 3.11.3 Access Arbitration
      4. 3.11.4 Memory Error Detection, Correction, and Error Handling
        1. 3.11.4.1 Error Detection and Correction
        2. 3.11.4.2 Error Handling
      5. 3.11.5 Application Test Hooks for Error Detection and Correction
      6. 3.11.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
    15. 3.15 SYSCTRL Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  SYNC_SOC_REGS Registers
      8. 3.15.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.15.9  DEV_CFG_REGS Registers
      10. 3.15.10 CLK_CFG_REGS Registers
      11. 3.15.11 CPU_SYS_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 MEM_CFG_REGS Registers
      14. 3.15.14 MEMORY_ERROR_REGS Registers
      15. 3.15.15 ROM_WAIT_STATE_REGS Registers
      16. 3.15.16 TEST_ERROR_REGS Registers
      17. 3.15.17 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 ECC Logic Self Test
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Open-Drain Configuration Requirements
    10. 8.10 Software
      1. 8.10.1 GPIO Examples
        1. 8.10.1.1 Device GPIO Setup
        2. 8.10.1.2 Device GPIO Toggle
        3. 8.10.1.3 Device GPIO Interrupt
        4. 8.10.1.4 External Interrupt (XINT)
      2. 8.10.2 LED Examples
    11. 8.11 GPIO Registers
      1. 8.11.1 GPIO Base Address Table
      2. 8.11.2 GPIO_CTRL_REGS Registers
      3. 8.11.3 GPIO_DATA_REGS Registers
      4. 8.11.4 GPIO_DATA_READ_REGS Registers
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 MCPWM and GPIO Output X-BAR
      1. 9.2.1 MCPWM X-BAR
        1. 9.2.1.1 MCPWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 PWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Digital Inputs on ADC Pins (AIOs)
    3. 11.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    4. 11.4 Analog Pins and Internal Connections
    5. 11.5 ASBSYS Registers
      1. 11.5.1 ASBSYS Base Address Table
      2. 11.5.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 ADC Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 ADC Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
        1. 12.2.4.1 Expected Conversion Results
        2. 12.2.4.2 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
        1. 12.3.2.1 Trigger Repeaters
          1. 12.3.2.1.1 Oversampling Mode
          2. 12.3.2.1.2 Re-trigger Spread
          3. 12.3.2.1.3 Trigger Repeater Configuration
            1. 12.3.2.1.3.1 Register Shadow Updates
          4. 12.3.2.1.4 Re-Trigger Logic
          5. 12.3.2.1.5 Multi-Path Triggering Behavior
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 Sample Capacitor Reset
      5. 12.3.5 ADC Input Models
      6. 12.3.6 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from MCPWM Trigger
      2. 12.4.2 Multiple Conversions from CPU Timer Trigger
      3. 12.4.3 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  EOC and Interrupt Operation
      1. 12.6.1 Interrupt Overflow
      2. 12.6.2 Continue to Interrupt Mode
      3. 12.6.3 Early Interrupt Configuration Mode
    7. 12.7  Post-Processing Blocks
      1. 12.7.1 PPB Offset Correction
      2. 12.7.2 PPB Error Calculation
      3. 12.7.3 PPB Limit Detection and Zero-Crossing Detection
    8. 12.8  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.8.1 Open Short Detection Implementation
      2. 12.8.2 Detecting an Open Input Pin
      3. 12.8.3 Detecting a Shorted Input Pin
    9. 12.9  Power-Up Sequence
    10. 12.10 ADC Calibration
      1. 12.10.1 ADC Zero Offset Calibration
    11. 12.11 ADC Timings
      1. 12.11.1 ADC Timing Diagrams
      2. 12.11.2 Post-Processing Block Timings
    12. 12.12 Additional Information
      1. 12.12.1 Choosing an Acquisition Window Duration
      2. 12.12.2 Result Register Mapping
      3. 12.12.3 Internal Temperature Sensor
      4. 12.12.4 Designing an External Reference Circuit
      5. 12.12.5 ADC-DAC Loopback Testing
      6. 12.12.6 Internal Test Mode
    13. 12.13 Software
      1. 12.13.1 ADC Examples
        1. 12.13.1.1 ADC Software Triggering
        2. 12.13.1.2 ADC MCPWM Triggering
        3. 12.13.1.3 ADC Temperature Sensor Conversion
        4. 12.13.1.4 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        5. 12.13.1.5 ADC PPB Offset (adc_ppb_offset)
        6. 12.13.1.6 ADC PPB Limits (adc_ppb_limits)
        7. 12.13.1.7 ADC SOC Oversampling
        8. 12.13.1.8 ADC Trigger Repeater Oversampling
    14. 12.14 ADC Registers
      1. 12.14.1 ADC Base Address Table
      2. 12.14.2 ADC_LITE_RESULT_REGS Registers
      3. 12.14.3 ADC_LITE_REGS Registers
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 CMPSS Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Digital Filter
      1. 13.4.1 Filter Initialization Sequence
    5. 13.5 Using the CMPSS
      1. 13.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 13.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.5.3 Calibrating the CMPSS
      4. 13.5.4 Enabling and Disabling the CMPSS Clock
    6. 13.6 CMPSS DAC Output
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
      2. 13.7.2 CMPSS_LITE Examples
        1. 13.7.2.1 CMPSSLITE Asynchronous Trip
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Address Table
      2. 13.8.2 CMPSS_LITE_REGS Registers
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Values
    4. 14.4  Modes of Operation
      1. 14.4.1 Buffer Mode
      2. 14.4.2 Standalone Mode
      3. 14.4.3 Non-inverting Mode
      4. 14.4.4 Subtractor Mode
    5. 14.5  External Filtering
      1. 14.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 14.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 14.6  Error Calibration
      1. 14.6.1 Offset Error
      2. 14.6.2 Gain Error
    7. 14.7  Chopping Feature
    8. 14.8  Enabling and Disabling the PGA Clock
    9. 14.9  Lock Register
    10. 14.10 Analog Front-End Integration
      1. 14.10.1 Analog-to-Digital Converter (ADC)
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 Comparator Subsystem (CMPSS)
      3. 14.10.3 Alternate Functions
    11. 14.11 Examples
      1. 14.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 14.11.2 Buffer Mode
      3. 14.11.3 Low-Side Current Sensing
      4. 14.11.4 Bidirectional Current Sensing
    12. 14.12 Software
      1. 14.12.1 PGA Examples
        1. 14.12.1.1 PGA CMPSSDAC-ADC External Loopback Example
    13. 14.13 PGA Registers
      1. 14.13.1 PGA Base Address Table
      2. 14.13.2 PGA_REGS Registers
  17. 15Multi-Channel Pulse Width Modulator (MCPWM)
    1. 15.1  Introduction
      1. 15.1.1 PWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  MCPWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
        4. 15.4.3.4 MCPWM SYNC Selection
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 15.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 15.4.6 Global Load
        1. 15.4.6.1 One-Shot Load Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-Band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  Trip-Zone (TZ) Submodule
      1. 15.8.1 Purpose of the Trip-Zone Submodule
      2. 15.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.8.2.1 Trip-Zone Configurations
      3. 15.8.3 Generating Trip Event Interrupts
    9. 15.9  Event-Trigger (ET) Submodule
      1. 15.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 15.10 PWM Crossbar (X-BAR)
    11. 15.11 Software
      1. 15.11.1 MCPWM Examples
        1. 15.11.1.1 MCPWM Basic PWM Generation and Updates
        2. 15.11.1.2 MCPWM Basic PWM Generation and Updates
        3. 15.11.1.3 MCPWM Basic PWM generation With DeadBand
        4. 15.11.1.4 MCPWM Basic PWM Generation and Updates without Sysconfig
        5. 15.11.1.5 MCPWM PWM Tripzone Feature Showcase
        6. 15.11.1.6 MCPWM Global Load Feature Showcase
        7. 15.11.1.7 MCPWM DMA Configuration for Dynamic PWM Control
    12. 15.12 MCPWM Registers
      1. 15.12.1 MCPWM Base Address Table
      2. 15.12.2 MCPWM_6CH_REGS Registers
      3. 15.12.3 MCPWM_2CH_REGS Registers
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1 Event Prescaler
      2. 16.5.2 Edge Polarity Select and Qualifier
      3. 16.5.3 Continuous/One-Shot Control
      4. 16.5.4 32-Bit Counter and Phase Control
      5. 16.5.5 CAP1-CAP4 Registers
      6. 16.5.6 eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7 Interrupt Control
      8. 16.5.8 Shadow Load and Lockout Control
      9. 16.5.9 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
    9. 16.9 ECAP Registers
      1. 16.9.1 ECAP Base Address Table
      2. 16.9.2 ECAP_REGS Registers
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  QMA Module
      1. 17.9.1 Modes of Operation
        1. 17.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 17.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 17.9.2 Interrupt and Error Generation
    10. 17.10 eQEP Interrupt Structure
    11. 17.11 Software
      1. 17.11.1 EQEP Examples
        1. 17.11.1.1 Frequency Measurement Using eQEP
        2. 17.11.1.2 Position and Speed Measurement Using eQEP
        3. 17.11.1.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 17.11.1.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 17.12 EQEP Registers
      1. 17.12.1 EQEP Base Address Table
      2. 17.12.2 EQEP_REGS Registers
  20. 18Universal Asynchronous Receiver/Transmitter (UART)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Functional Description
      1. 18.2.1 Transmit and Receive Logic
      2. 18.2.2 Baud-Rate Generation
      3. 18.2.3 Data Transmission
      4. 18.2.4 Serial IR (SIR)
      5. 18.2.5 9-Bit UART Mode
      6. 18.2.6 FIFO Operation
      7. 18.2.7 Interrupts
      8. 18.2.8 Loopback Operation
      9. 18.2.9 DMA Operation
        1. 18.2.9.1 Receiving Data Using UART with DMA
        2. 18.2.9.2 Transmitting Data Using UART with DMA
    3. 18.3 Initialization and Configuration
    4. 18.4 Software
      1. 18.4.1 UART Examples
        1. 18.4.1.1 UART Echoback
        2. 18.4.1.2 UART Loopback
        3. 18.4.1.3 UART Loopback with interrupt
        4. 18.4.1.4 UART Digital Loopback with DMA
    5. 18.5 UART Registers
      1. 18.5.1 UART Base Address Table
      2. 18.5.2 UART_REGS Registers
      3. 18.5.3 UART_REGS_WRITE Registers
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
      4. 19.2.4 DMA Support
    3. 19.3 SPI Operation
      1. 19.3.1  Introduction to Operation
      2. 19.3.2  Controller Mode
      3. 19.3.3  Peripheral Mode
      4. 19.3.4  Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5  Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6  SPI Clocking Schemes
      7. 19.3.7  SPI FIFO Description
      8. 19.3.8  SPI DMA Transfers
        1. 19.3.8.1 Transmitting Data Using SPI with DMA
        2. 19.3.8.2 Receiving Data Using SPI with DMA
      9. 19.3.9  SPI High-Speed Mode
      10. 19.3.10 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Controller Mode Transmit
        2.       679
          1. 19.4.5.2.1 3-Wire Controller Mode Receive
        3.       681
          1. 19.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       683
          1. 19.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI Digital Loopback with DMA
        4. 19.5.1.4 SPI EEPROM
        5. 19.5.1.5 SPI DMA EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Controller Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Clock Stretching
      10. 20.3.10 Arbitration
      11. 20.3.11 Digital Loopback Mode
      12. 20.3.12 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Registers to Driverlib Functions
      2. 20.6.2 I2C Examples
        1. 20.6.2.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.2.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.2.3 I2C Digital Loopback with FIFO Interrupts
        4. 20.6.2.4 I2C EEPROM
        5. 20.6.2.5 I2C EEPROM
        6. 20.6.2.6 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Address Table
      2. 20.7.2 I2C_REGS Registers
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
  24. 22Revision History

3.15.14 MEMORY_ERROR_REGS Registers

Table 3-171 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset addresses not listed in Table 3-171 should be considered as reserved locations and the register contents should not be modified.

Table 3-171 MEMORY_ERROR_REGS Registers
OffsetAcronymRegister NameWrite Protection
0hUCERRFLGUncorrectable Error Flag Register
2hUCERRSETUncorrectable Error Flag Set RegisterEALLOW
4hUCERRCLRUncorrectable Error Flag Clear RegisterEALLOW
6hUCCPUREADDRUncorrectable CPU Error Address
8hUCDMAREADDRUncorrectable DMA Error Address
10hFLUCERRSTATUSFlash read uncorrectable ecc err status
12hFLCERRSTATUSFlash read correctable ecc err status
20hCERRFLGCorrectable Error Flag Register
22hCERRSETCorrectable Error Flag Set Register
24hCERRCLRCorrectable Error Flag Clear Register
26hCCPUREADDRCorrectable CPU Error Address
28hCDMAREADDRCorrectable DMA Error Address
30hCERRCNTCorrectable Error Count Register
32hCERRTHRESCorrectable Error Threshold Value RegisterEALLOW
34hCEINTFLGCorrectable Error Interrupt Flag Status Register
36hCEINTCLRCorrectable Error Interrupt Flag Clear RegisterEALLOW
38hCEINTSETCorrectable Error Interrupt Flag Set RegisterEALLOW
3AhCEINTENCorrectable Error Interrupt Enable RegisterEALLOW

Complex bit access types are encoded to fit into small table cells. Table 3-172 shows the codes that are used for access types in this section.

Table 3-172 MEMORY_ERROR_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.15.14.1 UCERRFLG Register (Offset = 0h) [Reset = 00000000h]

UCERRFLG is shown in Figure 3-145 and described in Table 3-173.

Return to the Summary Table.

Uncorrectable Error Flag Register

Figure 3-145 UCERRFLG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERRCPU_READ_ERR
R-0-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-173 UCERRFLG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1DMA_READ_ERRR0hDMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.

Reset type: SYSRSn

0CPU_READ_ERRR0hCPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.

Reset type: SYSRSn

3.15.14.2 UCERRSET Register (Offset = 2h) [Reset = 00000000h]

UCERRSET is shown in Figure 3-146 and described in Table 3-174.

Return to the Summary Table.

Uncorrectable Error Flag Set Register

Figure 3-146 UCERRSET Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERRCPU_READ_ERR
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 3-174 UCERRSET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR-0/W1S0hReserved
4RESERVEDR-0/W1S0hReserved
3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1DMA_READ_ERRR-0/W1S0hDMA Uncorrectable Read Error Flag Set
0: No Error.
1: DMA Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled

Reset type: SYSRSn

0CPU_READ_ERRR-0/W1S0hCPU Uncorrectable Read Error Flag Set
0: No Error.
1: CPU Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled

Reset type: SYSRSn

3.15.14.3 UCERRCLR Register (Offset = 4h) [Reset = 00000000h]

UCERRCLR is shown in Figure 3-147 and described in Table 3-175.

Return to the Summary Table.

Uncorrectable Error Flag Clear Register

Figure 3-147 UCERRCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERRCPU_READ_ERR
R-0-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 3-175 UCERRCLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR-0/W1C0hReserved
4RESERVEDR-0/W1C0hReserved
3RESERVEDR-0/W1C0hReserved
2RESERVEDR-0/W1C0hReserved
1DMA_READ_ERRR-0/W1C0hDMA Uncorrectable Read Error Flag clear
0: No Error.
1:DMA Read error Flag in UCERRFLG register will be cleared

Reset type: SYSRSn

0CPU_READ_ERRR-0/W1C0hCPU Uncorrectable Read Error Flag clear
0: No Error.
1: CPU Read error Flag in UCERRFLG register will be cleared

Reset type: SYSRSn

3.15.14.4 UCCPUREADDR Register (Offset = 6h) [Reset = 00000000h]

UCCPUREADDR is shown in Figure 3-148 and described in Table 3-176.

Return to the Summary Table.

Uncorrectable CPU Error Address

Figure 3-148 UCCPUREADDR Register
313029282726252423222120191817161514131211109876543210
UCCPUREADDR
R-0h
Table 3-176 UCCPUREADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0UCCPUREADDRR0hThis register captures the address location for which CPU read/fetch access resulted in uncorrectable ECC/Parity error.

Reset type: SYSRSn

3.15.14.5 UCDMAREADDR Register (Offset = 8h) [Reset = 00000000h]

UCDMAREADDR is shown in Figure 3-149 and described in Table 3-177.

Return to the Summary Table.

Uncorrectable DMA Error Address

Figure 3-149 UCDMAREADDR Register
313029282726252423222120191817161514131211109876543210
UCDMAREADDR
R-0h
Table 3-177 UCDMAREADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0UCDMAREADDRR0hThis register captures the address location for which DMA read/fetch access resulted in uncorrectable ECC/Parity error.

Reset type: SYSRSn

3.15.14.6 FLUCERRSTATUS Register (Offset = 10h) [Reset = 00000000h]

FLUCERRSTATUS is shown in Figure 3-150 and described in Table 3-178.

Return to the Summary Table.

Flash read uncorrectable ecc err status

Figure 3-150 FLUCERRSTATUS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDDIAG_H_FAILUNC_ERR_H
R-0hR-0hR-0h
76543210
RESERVEDDIAG_L_FAILUNC_ERR_L
R-0hR-0hR-0h
Table 3-178 FLUCERRSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9DIAG_H_FAILR0hStatus of ECC diagnosic logic .
0 : Status of diagnostic error if there is no single/mutli bit error on the output of ECC check.
1 : Status of diagnostic error if there is single/mutli bit error on the output of ECC check.
Note :
The field gets updated along with UNC_ERR_H
This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
UCERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

8UNC_ERR_HR0hUncorrectable error. A value of 1 indicates that an un-correctable error occurred in upper 64bits of a 128-bit aligned address.
Note :
This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
UCERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

7-2RESERVEDR0hReserved
1DIAG_L_FAILR0hStatus of ECC diagnosic logic .
0 : Status of diagnostic error if there is no single/mutli bit error on the output of ECC check.
1 : Status of diagnostic error if there is single/mutli bit error on the output of ECC check.
Note :
The field gets updated along with UNC_ERR_L
This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
UCERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

0UNC_ERR_LR0hUncorrectable error. A value of 1 indicates that an un-correctable error occurred in lower 64bits of a 128-bit aligned address.
Note :
This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
UCERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

3.15.14.7 FLCERRSTATUS Register (Offset = 12h) [Reset = 00000000h]

FLCERRSTATUS is shown in Figure 3-151 and described in Table 3-179.

Return to the Summary Table.

Flash read correctable ecc err status

Figure 3-151 FLCERRSTATUS Register
3130292827262524
RESERVEDERR_TYPE_HERR_POS_H
R-0hR-0hR-0h
2322212019181716
ERR_POS_HERR_TYPE_LERR_POS_L
R-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDFAIL_1_HFAIL_0_HRESERVEDFAIL_1_LFAIL_0_L
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-179 FLCERRSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ERR_TYPE_HR0hError type
0 Indicates that a single bit error occured in upper 64 data bits of a 128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of upper 64bits of a 128-bit aligned address.
Note :
This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this field.

Reset type: SYSRSn

28-23ERR_POS_HR0hError position. Bit position of the single bit error in upper 64bits of a 128-bit aligned address. The position is interpreted depending on whether the ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7, else it could range from 0 to 63.
Note :
This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this field.

Reset type: SYSRSn

22ERR_TYPE_LR0hError type
0 Indicates that a single bit error occured in lower 64 data bits of a 128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of lower 64bits of a 128-bit aligned address.
Note :
This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this field.

Reset type: SYSRSn

21-16ERR_POS_LR0hError position. Bit position of the single bit error in lower 64bits of a 128-bit aligned address. The position is interpreted depending on whether the ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7, else it could range from 0 to 63.
Note :
This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this field.

Reset type: SYSRSn

15-6RESERVEDR0hReserved
5RESERVEDR0hReserved
4FAIL_1_HR0hFail on 1.
0 Fail on 1 single bit error did not occur in upper 64bits of a 128-bit aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper 64bits of a 128-bit aligned address and the corrected value was 1.
Note :
This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

3FAIL_0_HR0hFail on 0.
0 Fail on 0 single bit error did not occur in upper 64bits of a 128-bit aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper 64bits of a 128-bit aligned address and the corrected value was 0.
Note :
This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

2RESERVEDR0hReserved
1FAIL_1_LR0hFail on 1.
0 Fail on 1 single bit error did not occur in lower 64bits of a 128-bit aligned address.
1 A value of 1 would indicate that a single bit error occurred in lower 64bits of a 128-bit aligned address and the corrected value was 1.
Note :
This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag CERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

0FAIL_0_LR0hFail on 0.
0 Fail on 0 single bit error did not occur in lower 64bits of 128-bit data.
1 Would indicate that a single bit error occurred in lower 64bits of a 128-bit aligned address and the corrected value was 0.
Note :
This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
CERRSET.CPURDERR has no effect on this flag.

Reset type: SYSRSn

3.15.14.8 CERRFLG Register (Offset = 20h) [Reset = 00000000h]

CERRFLG is shown in Figure 3-152 and described in Table 3-180.

Return to the Summary Table.

Correctable Error Flag Register

Figure 3-152 CERRFLG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERRCPU_READ_ERR
R-0-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-180 CERRFLG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1DMA_READ_ERRR0hDMA correctable Read Error Flag
0: No Error.
1: correctable error occurred during DMA read.

Reset type: SYSRSn

0CPU_READ_ERRR0hCPU correctable Read Error Flag
0: No Error.
1: correctable error occurred during CPU read.

Reset type: SYSRSn

3.15.14.9 CERRSET Register (Offset = 22h) [Reset = 00000000h]

CERRSET is shown in Figure 3-153 and described in Table 3-181.

Return to the Summary Table.

Correctable Error Flag Set Register

Figure 3-153 CERRSET Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERR_SETCPU_READ_ERR_SET
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 3-181 CERRSET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR-0/W1S0hReserved
4RESERVEDR-0/W1S0hReserved
3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1DMA_READ_ERR_SETR-0/W1S0hDMA correctable Read Error Flag Set
0: No Error.
1: DMA Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled

Reset type: SYSRSn

0CPU_READ_ERR_SETR-0/W1S0hCPU correctable Read Error Flag Set
0: No Error.
1:CPU Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled

Reset type: SYSRSn

3.15.14.10 CERRCLR Register (Offset = 24h) [Reset = 00000000h]

CERRCLR is shown in Figure 3-154 and described in Table 3-182.

Return to the Summary Table.

Correctable Error Flag Clear Register

Figure 3-154 CERRCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDDMA_READ_ERR_CLRCPU_READ_ERR_CLR
R-0-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 3-182 CERRCLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR-0/W1C0hReserved
4RESERVEDR-0/W1C0hReserved
3RESERVEDR-0/W1C0hReserved
2RESERVEDR-0/W1C0hReserved
1DMA_READ_ERR_CLRR-0/W1C0hDMA correctable Read Error Flag clear
0: No Error.
1: DMA Read error Flag in CERRFLG register will be cleared

Reset type: SYSRSn

0CPU_READ_ERR_CLRR-0/W1C0hCPU correctable Read Error Flag clear
0: No Error.
1: CPU Read error Flag in CERRFLG register will be cleared

Reset type: SYSRSn

3.15.14.11 CCPUREADDR Register (Offset = 26h) [Reset = 00000000h]

CCPUREADDR is shown in Figure 3-155 and described in Table 3-183.

Return to the Summary Table.

Correctable CPU Error Address

Figure 3-155 CCPUREADDR Register
313029282726252423222120191817161514131211109876543210
CCPUREADDR
R-0h
Table 3-183 CCPUREADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0CCPUREADDRR0hThis register captures the address location for which CPU read/fetch access resulted in correctable ECC/Parity error.

Reset type: SYSRSn

3.15.14.12 CDMAREADDR Register (Offset = 28h) [Reset = 00000000h]

CDMAREADDR is shown in Figure 3-156 and described in Table 3-184.

Return to the Summary Table.

Correctable DMA Error Address

Figure 3-156 CDMAREADDR Register
313029282726252423222120191817161514131211109876543210
CDMAREADDR
R-0h
Table 3-184 CDMAREADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0CDMAREADDRR0hThis register captures the address location for which DMA read/fetch access resulted in correctable ECC/Parity error.

Reset type: SYSRSn

3.15.14.13 CERRCNT Register (Offset = 30h) [Reset = 00000000h]

CERRCNT is shown in Figure 3-157 and described in Table 3-185.

Return to the Summary Table.

Correctable Error Count Register

Figure 3-157 CERRCNT Register
313029282726252423222120191817161514131211109876543210
CERRCNT
R-0h
Table 3-185 CERRCNT Register Field Descriptions
BitFieldTypeResetDescription
31-0CERRCNTR0hThis register holds the count of how many times correctable error occurred.

Reset type: SYSRSn

3.15.14.14 CERRTHRES Register (Offset = 32h) [Reset = 00000000h]

CERRTHRES is shown in Figure 3-158 and described in Table 3-186.

Return to the Summary Table.

Correctable Error Threshold Value Register

Figure 3-158 CERRTHRES Register
313029282726252423222120191817161514131211109876543210
RESERVEDCERRTHRES
R-0-0hR/W-0h
Table 3-186 CERRTHRES Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0CERRTHRESR/W0hWhen value in CERRCNT register is greater than value configured in this register, corretable interrupt gets generated, if enabled.

Reset type: SYSRSn

3.15.14.15 CEINTFLG Register (Offset = 34h) [Reset = 00000000h]

CEINTFLG is shown in Figure 3-159 and described in Table 3-187.

Return to the Summary Table.

Correctable Error Interrupt Flag Status Register

Figure 3-159 CEINTFLG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCEINTFLAG
R-0-0hR-0h
Table 3-187 CEINTFLG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0CEINTFLAGR0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in CERR_THR register.
1: Total correctable errors >= Threshold value configured in CERR_THR register.

Reset type: SYSRSn

3.15.14.16 CEINTCLR Register (Offset = 36h) [Reset = 00000000h]

CEINTCLR is shown in Figure 3-160 and described in Table 3-188.

Return to the Summary Table.

Correctable Error Interrupt Flag Clear Register

Figure 3-160 CEINTCLR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCEINTCLR
R-0-0hR-0/W1S-0h
Table 3-188 CEINTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0CEINTCLRR-0/W1S0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register will be cleared.

Reset type: SYSRSn

3.15.14.17 CEINTSET Register (Offset = 38h) [Reset = 00000000h]

CEINTSET is shown in Figure 3-161 and described in Table 3-189.

Return to the Summary Table.

Correctable Error Interrupt Flag Set Register

Figure 3-161 CEINTSET Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCEINTSET
R-0-0hR-0/W1S-0h
Table 3-189 CEINTSET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0CEINTSETR-0/W1S0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register will be set and interrupt will be generated if enabled.

Reset type: SYSRSn

3.15.14.18 CEINTEN Register (Offset = 3Ah) [Reset = 00000000h]

CEINTEN is shown in Figure 3-162 and described in Table 3-190.

Return to the Summary Table.

Correctable Error Interrupt Enable Register

Figure 3-162 CEINTEN Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCEINTEN
R-0-0hR/W-0h
Table 3-190 CEINTEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0CEINTENR/W0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.

Reset type: SYSRSn