SPRUJD3A July   2025  – October 2025 F28E120SB , F28E120SC

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Power-On Reset (POR)
      4. 3.4.4  Brown-Out-Reset (BOR)
      5. 3.4.5  Watchdog Reset (WDRS)
      6. 3.4.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.4.7  Debugger Reset (SYSRS)
      8. 3.4.8  DCSM Safe Code Copy Reset (SCCRESET)
      9. 3.4.9  Simulate External Reset (SIMRESET.XRS)
      10. 3.4.10 Simulate CPU Reset (SIMRESET_CPU1RS)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection Logic
        2. 3.6.3.2 Flash Uncorrectable ECC Error
        3. 3.6.3.3 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (SYSOSC)
        2. 3.7.1.2 Backup Wide-Range Oscillator (WROSC)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power-Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Dedicated RAM (Mx RAM)
      2. 3.11.2 Global Shared RAM (GSx RAM)
      3. 3.11.3 Access Arbitration
      4. 3.11.4 Memory Error Detection, Correction, and Error Handling
        1. 3.11.4.1 Error Detection and Correction
        2. 3.11.4.2 Error Handling
      5. 3.11.5 Application Test Hooks for Error Detection and Correction
      6. 3.11.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
    15. 3.15 SYSCTRL Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  CPUTIMER_REGS Registers
      3. 3.15.3  PIE_CTRL_REGS Registers
      4. 3.15.4  WD_REGS Registers
      5. 3.15.5  NMI_INTRUPT_REGS Registers
      6. 3.15.6  XINT_REGS Registers
      7. 3.15.7  SYNC_SOC_REGS Registers
      8. 3.15.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.15.9  DEV_CFG_REGS Registers
      10. 3.15.10 CLK_CFG_REGS Registers
      11. 3.15.11 CPU_SYS_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 MEM_CFG_REGS Registers
      14. 3.15.14 MEMORY_ERROR_REGS Registers
      15. 3.15.15 ROM_WAIT_STATE_REGS Registers
      16. 3.15.16 TEST_ERROR_REGS Registers
      17. 3.15.17 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 ECC Logic Self Test
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Open-Drain Configuration Requirements
    10. 8.10 Software
      1. 8.10.1 GPIO Examples
        1. 8.10.1.1 Device GPIO Setup
        2. 8.10.1.2 Device GPIO Toggle
        3. 8.10.1.3 Device GPIO Interrupt
        4. 8.10.1.4 External Interrupt (XINT)
      2. 8.10.2 LED Examples
    11. 8.11 GPIO Registers
      1. 8.11.1 GPIO Base Address Table
      2. 8.11.2 GPIO_CTRL_REGS Registers
      3. 8.11.3 GPIO_DATA_REGS Registers
      4. 8.11.4 GPIO_DATA_READ_REGS Registers
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 MCPWM and GPIO Output X-BAR
      1. 9.2.1 MCPWM X-BAR
        1. 9.2.1.1 MCPWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 PWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
  13. 11Analog Subsystem
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Digital Inputs on ADC Pins (AIOs)
    3. 11.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    4. 11.4 Analog Pins and Internal Connections
    5. 11.5 ASBSYS Registers
      1. 11.5.1 ASBSYS Base Address Table
      2. 11.5.2 ANALOG_SUBSYS_REGS Registers
  14. 12Analog-to-Digital Converter (ADC)
    1. 12.1  Introduction
      1. 12.1.1 Features
      2. 12.1.2 ADC Related Collateral
      3. 12.1.3 Block Diagram
    2. 12.2  ADC Configurability
      1. 12.2.1 ADC Clock Configuration
      2. 12.2.2 Resolution
      3. 12.2.3 Voltage Reference
        1. 12.2.3.1 External Reference Mode
        2. 12.2.3.2 Internal Reference Mode
        3. 12.2.3.3 Selecting Reference Mode
      4. 12.2.4 Signal Mode
        1. 12.2.4.1 Expected Conversion Results
        2. 12.2.4.2 Interpreting Conversion Results
    3. 12.3  SOC Principle of Operation
      1. 12.3.1 SOC Configuration
      2. 12.3.2 Trigger Operation
        1. 12.3.2.1 Trigger Repeaters
          1. 12.3.2.1.1 Oversampling Mode
          2. 12.3.2.1.2 Re-trigger Spread
          3. 12.3.2.1.3 Trigger Repeater Configuration
            1. 12.3.2.1.3.1 Register Shadow Updates
          4. 12.3.2.1.4 Re-Trigger Logic
          5. 12.3.2.1.5 Multi-Path Triggering Behavior
      3. 12.3.3 ADC Acquisition (Sample and Hold) Window
      4. 12.3.4 Sample Capacitor Reset
      5. 12.3.5 ADC Input Models
      6. 12.3.6 Channel Selection
    4. 12.4  SOC Configuration Examples
      1. 12.4.1 Single Conversion from MCPWM Trigger
      2. 12.4.2 Multiple Conversions from CPU Timer Trigger
      3. 12.4.3 Software Triggering of SOCs
    5. 12.5  ADC Conversion Priority
    6. 12.6  EOC and Interrupt Operation
      1. 12.6.1 Interrupt Overflow
      2. 12.6.2 Continue to Interrupt Mode
      3. 12.6.3 Early Interrupt Configuration Mode
    7. 12.7  Post-Processing Blocks
      1. 12.7.1 PPB Offset Correction
      2. 12.7.2 PPB Error Calculation
      3. 12.7.3 PPB Limit Detection and Zero-Crossing Detection
    8. 12.8  Opens/Shorts Detection Circuit (OSDETECT)
      1. 12.8.1 Open Short Detection Implementation
      2. 12.8.2 Detecting an Open Input Pin
      3. 12.8.3 Detecting a Shorted Input Pin
    9. 12.9  Power-Up Sequence
    10. 12.10 ADC Calibration
      1. 12.10.1 ADC Zero Offset Calibration
    11. 12.11 ADC Timings
      1. 12.11.1 ADC Timing Diagrams
      2. 12.11.2 Post-Processing Block Timings
    12. 12.12 Additional Information
      1. 12.12.1 Choosing an Acquisition Window Duration
      2. 12.12.2 Result Register Mapping
      3. 12.12.3 Internal Temperature Sensor
      4. 12.12.4 Designing an External Reference Circuit
      5. 12.12.5 ADC-DAC Loopback Testing
      6. 12.12.6 Internal Test Mode
    13. 12.13 Software
      1. 12.13.1 ADC Examples
        1. 12.13.1.1 ADC Software Triggering
        2. 12.13.1.2 ADC MCPWM Triggering
        3. 12.13.1.3 ADC Temperature Sensor Conversion
        4. 12.13.1.4 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        5. 12.13.1.5 ADC PPB Offset (adc_ppb_offset)
        6. 12.13.1.6 ADC PPB Limits (adc_ppb_limits)
        7. 12.13.1.7 ADC SOC Oversampling
        8. 12.13.1.8 ADC Trigger Repeater Oversampling
    14. 12.14 ADC Registers
      1. 12.14.1 ADC Base Address Table
      2. 12.14.2 ADC_LITE_RESULT_REGS Registers
      3. 12.14.3 ADC_LITE_REGS Registers
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 CMPSS Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Digital Filter
      1. 13.4.1 Filter Initialization Sequence
    5. 13.5 Using the CMPSS
      1. 13.5.1 LATCHCLR, and MCPWMSYNCPER Signals
      2. 13.5.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.5.3 Calibrating the CMPSS
      4. 13.5.4 Enabling and Disabling the CMPSS Clock
    6. 13.6 CMPSS DAC Output
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
      2. 13.7.2 CMPSS_LITE Examples
        1. 13.7.2.1 CMPSSLITE Asynchronous Trip
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Address Table
      2. 13.8.2 CMPSS_LITE_REGS Registers
  16. 14Programmable Gain Amplifier (PGA)
    1. 14.1  Programmable Gain Amplifier (PGA) Overview
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2  Linear Output Range
    3. 14.3  Gain Values
    4. 14.4  Modes of Operation
      1. 14.4.1 Buffer Mode
      2. 14.4.2 Standalone Mode
      3. 14.4.3 Non-inverting Mode
      4. 14.4.4 Subtractor Mode
    5. 14.5  External Filtering
      1. 14.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 14.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 14.6  Error Calibration
      1. 14.6.1 Offset Error
      2. 14.6.2 Gain Error
    7. 14.7  Chopping Feature
    8. 14.8  Enabling and Disabling the PGA Clock
    9. 14.9  Lock Register
    10. 14.10 Analog Front-End Integration
      1. 14.10.1 Analog-to-Digital Converter (ADC)
        1. 14.10.1.1 Unfiltered Acquisition Window
        2. 14.10.1.2 Filtered Acquisition Window
      2. 14.10.2 Comparator Subsystem (CMPSS)
      3. 14.10.3 Alternate Functions
    11. 14.11 Examples
      1. 14.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 14.11.2 Buffer Mode
      3. 14.11.3 Low-Side Current Sensing
      4. 14.11.4 Bidirectional Current Sensing
    12. 14.12 Software
      1. 14.12.1 PGA Examples
        1. 14.12.1.1 PGA CMPSSDAC-ADC External Loopback Example
    13. 14.13 PGA Registers
      1. 14.13.1 PGA Base Address Table
      2. 14.13.2 PGA_REGS Registers
  17. 15Multi-Channel Pulse Width Modulator (MCPWM)
    1. 15.1  Introduction
      1. 15.1.1 PWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  MCPWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
        4. 15.4.3.4 MCPWM SYNC Selection
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple MCPWM Modules
      5. 15.4.5 Time-Base Counter Modes and Timing Waveforms
      6. 15.4.6 Global Load
        1. 15.4.6.1 One-Shot Load Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-Band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  Trip-Zone (TZ) Submodule
      1. 15.8.1 Purpose of the Trip-Zone Submodule
      2. 15.8.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.8.2.1 Trip-Zone Configurations
      3. 15.8.3 Generating Trip Event Interrupts
    9. 15.9  Event-Trigger (ET) Submodule
      1. 15.9.1 Operational Overview of the MCPWM Event-Trigger Submodule
    10. 15.10 PWM Crossbar (X-BAR)
    11. 15.11 Software
      1. 15.11.1 MCPWM Examples
        1. 15.11.1.1 MCPWM Basic PWM Generation and Updates
        2. 15.11.1.2 MCPWM Basic PWM Generation and Updates
        3. 15.11.1.3 MCPWM Basic PWM generation With DeadBand
        4. 15.11.1.4 MCPWM Basic PWM Generation and Updates without Sysconfig
        5. 15.11.1.5 MCPWM PWM Tripzone Feature Showcase
        6. 15.11.1.6 MCPWM Global Load Feature Showcase
        7. 15.11.1.7 MCPWM DMA Configuration for Dynamic PWM Control
    12. 15.12 MCPWM Registers
      1. 15.12.1 MCPWM Base Address Table
      2. 15.12.2 MCPWM_6CH_REGS Registers
      3. 15.12.3 MCPWM_2CH_REGS Registers
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1 Event Prescaler
      2. 16.5.2 Edge Polarity Select and Qualifier
      3. 16.5.3 Continuous/One-Shot Control
      4. 16.5.4 32-Bit Counter and Phase Control
      5. 16.5.5 CAP1-CAP4 Registers
      6. 16.5.6 eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7 Interrupt Control
      8. 16.5.8 Shadow Load and Lockout Control
      9. 16.5.9 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
    9. 16.9 ECAP Registers
      1. 16.9.1 ECAP Base Address Table
      2. 16.9.2 ECAP_REGS Registers
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  QMA Module
      1. 17.9.1 Modes of Operation
        1. 17.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 17.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 17.9.2 Interrupt and Error Generation
    10. 17.10 eQEP Interrupt Structure
    11. 17.11 Software
      1. 17.11.1 EQEP Examples
        1. 17.11.1.1 Frequency Measurement Using eQEP
        2. 17.11.1.2 Position and Speed Measurement Using eQEP
        3. 17.11.1.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 17.11.1.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 17.12 EQEP Registers
      1. 17.12.1 EQEP Base Address Table
      2. 17.12.2 EQEP_REGS Registers
  20. 18Universal Asynchronous Receiver/Transmitter (UART)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 Functional Description
      1. 18.2.1 Transmit and Receive Logic
      2. 18.2.2 Baud-Rate Generation
      3. 18.2.3 Data Transmission
      4. 18.2.4 Serial IR (SIR)
      5. 18.2.5 9-Bit UART Mode
      6. 18.2.6 FIFO Operation
      7. 18.2.7 Interrupts
      8. 18.2.8 Loopback Operation
      9. 18.2.9 DMA Operation
        1. 18.2.9.1 Receiving Data Using UART with DMA
        2. 18.2.9.2 Transmitting Data Using UART with DMA
    3. 18.3 Initialization and Configuration
    4. 18.4 Software
      1. 18.4.1 UART Examples
        1. 18.4.1.1 UART Echoback
        2. 18.4.1.2 UART Loopback
        3. 18.4.1.3 UART Loopback with interrupt
        4. 18.4.1.4 UART Digital Loopback with DMA
    5. 18.5 UART Registers
      1. 18.5.1 UART Base Address Table
      2. 18.5.2 UART_REGS Registers
      3. 18.5.3 UART_REGS_WRITE Registers
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
      4. 19.2.4 DMA Support
    3. 19.3 SPI Operation
      1. 19.3.1  Introduction to Operation
      2. 19.3.2  Controller Mode
      3. 19.3.3  Peripheral Mode
      4. 19.3.4  Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5  Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6  SPI Clocking Schemes
      7. 19.3.7  SPI FIFO Description
      8. 19.3.8  SPI DMA Transfers
        1. 19.3.8.1 Transmitting Data Using SPI with DMA
        2. 19.3.8.2 Receiving Data Using SPI with DMA
      9. 19.3.9  SPI High-Speed Mode
      10. 19.3.10 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Controller Mode Transmit
        2.       679
          1. 19.4.5.2.1 3-Wire Controller Mode Receive
        3.       681
          1. 19.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       683
          1. 19.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI Digital Loopback with DMA
        4. 19.5.1.4 SPI EEPROM
        5. 19.5.1.5 SPI DMA EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Controller Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Clock Stretching
      10. 20.3.10 Arbitration
      11. 20.3.11 Digital Loopback Mode
      12. 20.3.12 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Registers to Driverlib Functions
      2. 20.6.2 I2C Examples
        1. 20.6.2.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.2.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.2.3 I2C Digital Loopback with FIFO Interrupts
        4. 20.6.2.4 I2C EEPROM
        5. 20.6.2.5 I2C EEPROM
        6. 20.6.2.6 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Address Table
      2. 20.7.2 I2C_REGS Registers
  23. 21Serial Communications Interface (SCI)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 SCI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2  Architecture
    3. 21.3  SCI Module Signal Summary
    4. 21.4  Configuring Device Pins
    5. 21.5  Multiprocessor and Asynchronous Communication Modes
    6. 21.6  SCI Programmable Data Format
    7. 21.7  SCI Multiprocessor Communication
      1. 21.7.1 Recognizing the Address Byte
      2. 21.7.2 Controlling the SCI TX and RX Features
      3. 21.7.3 Receipt Sequence
    8. 21.8  Idle-Line Multiprocessor Mode
      1. 21.8.1 Idle-Line Mode Steps
      2. 21.8.2 Block Start Signal
      3. 21.8.3 Wake-Up Temporary (WUT) Flag
        1. 21.8.3.1 Sending a Block Start Signal
      4. 21.8.4 Receiver Operation
    9. 21.9  Address-Bit Multiprocessor Mode
      1. 21.9.1 Sending an Address
    10. 21.10 SCI Communication Format
      1. 21.10.1 Receiver Signals in Communication Modes
      2. 21.10.2 Transmitter Signals in Communication Modes
    11. 21.11 SCI Port Interrupts
      1. 21.11.1 Break Detect
    12. 21.12 SCI Baud Rate Calculations
    13. 21.13 SCI Enhanced Features
      1. 21.13.1 SCI FIFO Description
      2. 21.13.2 SCI Auto-Baud
      3. 21.13.3 Autobaud-Detect Sequence
    14. 21.14 Software
      1. 21.14.1 SCI Examples
        1. 21.14.1.1 Tune Baud Rate via UART Example
        2. 21.14.1.2 SCI FIFO Digital Loop Back
        3. 21.14.1.3 SCI Digital Loop Back with Interrupts
        4. 21.14.1.4 SCI Echoback
        5. 21.14.1.5 stdout redirect example
    15. 21.15 SCI Registers
      1. 21.15.1 SCI Base Address Table
      2. 21.15.2 SCI_REGS Registers
  24. 22Revision History

12.14.3 ADC_LITE_REGS Registers

Table 12-38 lists the memory-mapped registers for the ADC_LITE_REGS registers. All register offset addresses not listed in Table 12-38 should be considered as reserved locations and the register contents should not be modified.

Table 12-38 ADC_LITE_REGS Registers
OffsetAcronymRegister NameWrite Protection
0hADCCTL1ADC Control 1 RegisterEALLOW
2hADCCTL2ADC Control 2 RegisterEALLOW
8hADCINTSELADC Interrupt 1, 2, 3 and 4 Selection RegisterEALLOW
AhADCDMAINTSELADC DMA Interrupt 1, 2, 3 and 4 Selection RegisterEALLOW
ChADCRAWINTFLGADC Raw Interrupt Flag Register
EhADCINTFLGADC Interrupt Flag Register
10hADCINTFLGFRCADC Interrupt Flag Force Register
12hADCINTFLGCLRADC Interrupt Flag Clear Register
14hADCINTOVFADC Interrupt Overflow Register
16hADCINTOVFCLRADC Interrupt Overflow Clear Register
18hADCSOCPRICTLADC SOC Priority Control RegisterEALLOW
1AhADCINTSOCSEL1ADC Interrupt SOC Selection 1 RegisterEALLOW
1EhADCSOCFLG1ADC SOC Flag 1 Register
20hADCSOCFRC1ADC SOC Force 1 Register
22hADCSOCOVF1ADC SOC Overflow 1 Register
24hADCSOCOVFCLR1ADC SOC Overflow Clear 1 Register
26hADCSOC0CTLADC SOC0 Control RegisterEALLOW
28hADCSOC1CTLADC SOC1 Control RegisterEALLOW
2AhADCSOC2CTLADC SOC2 Control RegisterEALLOW
2ChADCSOC3CTLADC SOC3 Control RegisterEALLOW
2EhADCSOC4CTLADC SOC4 Control RegisterEALLOW
30hADCSOC5CTLADC SOC5 Control RegisterEALLOW
32hADCSOC6CTLADC SOC6 Control RegisterEALLOW
34hADCSOC7CTLADC SOC7 Control RegisterEALLOW
36hADCSOC8CTLADC SOC8 Control RegisterEALLOW
38hADCSOC9CTLADC SOC9 Control RegisterEALLOW
3AhADCSOC10CTLADC SOC10 Control RegisterEALLOW
3ChADCSOC11CTLADC SOC11 Control RegisterEALLOW
3EhADCSOC12CTLADC SOC12 Control RegisterEALLOW
40hADCSOC13CTLADC SOC13 Control RegisterEALLOW
42hADCSOC14CTLADC SOC14 Control RegisterEALLOW
44hADCSOC15CTLADC SOC15 Control RegisterEALLOW
66hADCEVTSTATADC Event Status Register
68hADCEVTCLRADC Event Clear Register
6AhADCEVTSELADC Event Selection RegisterEALLOW
6ChADCEVTINTSELADC Event Interrupt Selection RegisterEALLOW
72hADCREVADC Revision Register
74hADCOFFTRIMADC Offset Trim Register 1EALLOW
80hADCPPB1CONFIGADC PPB{#} Config RegisterEALLOW
84hADCPPB1OFFCALADC PPB1 Offset Calibration RegisterEALLOW
86hADCPPB1OFFREFADC PPB1 Offset Reference Register
88hADCPPB1TRIPHIADC PPB1 Trip High RegisterEALLOW
8AhADCPPB1TRIPLOADC PPB1 Trip Low/Trigger Time Stamp RegisterEALLOW
90hADCPPB2CONFIGADC PPB{#} Config RegisterEALLOW
94hADCPPB2OFFCALADC PPB2 Offset Calibration RegisterEALLOW
96hADCPPB2OFFREFADC PPB2 Offset Reference Register
98hADCPPB2TRIPHIADC PPB2 Trip High RegisterEALLOW
9AhADCPPB2TRIPLOADC PPB2 Trip Low/Trigger Time Stamp RegisterEALLOW
A0hADCPPB3CONFIGADC PPB{#} Config RegisterEALLOW
A4hADCPPB3OFFCALADC PPB3 Offset Calibration RegisterEALLOW
A6hADCPPB3OFFREFADC PPB3 Offset Reference Register
A8hADCPPB3TRIPHIADC PPB3 Trip High RegisterEALLOW
AAhADCPPB3TRIPLOADC PPB3 Trip Low/Trigger Time Stamp RegisterEALLOW
C0hADCINTCYCLEADC Early Interrupt Generation CycleEALLOW
C2hADCINLTRIM1ADC Linearity Trim 1 RegisterEALLOW
C4hADCINLTRIM2ADC Linearity Trim 2 RegisterEALLOW
CEhADCREV2ADC Wrapper Revision Register
E0hREP1CTLADC Trigger Repeater 1 Control RegisterEALLOW
E2hREP1NADC Trigger Repeater 1 N Select RegisterEALLOW
E6hREP1SPREADADC Trigger Repeater 1 Spread Select RegisterEALLOW
E8hREP1FRCADC Trigger Repeater 1 Software Force RegisterEALLOW
100hADCPPB1LIMITADC PPB1Conversion Count Limit RegisterEALLOW
102hADCPPBP1PCOUNTADC PPB1 Partial Conversion Count Register
104hADCPPB1CONFIG2ADC PPB1 Sum Shift Register
106hADCPPB1PSUMADC PPB1 Partial Sum Register

Complex bit access types are encoded to fit into small table cells. Table 12-39 shows the codes that are used for access types in this section.

Table 12-39 ADC_LITE_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

12.14.3.1 ADCCTL1 Register (Offset = 0h) [Reset = 00000000h]

ADCCTL1 is shown in Figure 12-39 and described in Table 12-40.

Return to the Summary Table.

ADC Control 1 Register

Figure 12-39 ADCCTL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDADCBSYRESERVEDADCBSYCHN
R-0hR-0hR-0hR-0h
76543210
ADCPWDNZRESERVEDINTPULSEPOSRESERVED
R/W-0hR-0hR/W-0hR-0h
Table 12-40 ADCCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13ADCBSYR0hADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample.

0 ADC is available to sample next channel
1 ADC is busy and cannot sample another channel

Reset type: SYSRSn

12RESERVEDR0hReserved
11-8ADCBSYCHNR0hADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated.
When ADCBSY=0: holds the value of the last converted SOC
When ADCBSY=1: reflects the SOC currently being processed
0h SOC0 is currently processing or was last SOC converted
1h SOC1 is currently processing or was last SOC converted
2h SOC2 is currently processing or was last SOC converted
3h SOC3 is currently processing or was last SOC converted
4h SOC4 is currently processing or was last SOC converted
5h SOC5 is currently processing or was last SOC converted
6h SOC6 is currently processing or was last SOC converted
7h SOC7 is currently processing or was last SOC converted
8h SOC8 is currently processing or was last SOC converted
9h SOC9 is currently processing or was last SOC converted
Ah SOC10 is currently processing or was last SOC converted
Bh SOC11 is currently processing or was last SOC converted
Ch SOC12 is currently processing or was last SOC converted
Dh SOC13 is currently processing or was last SOC converted
Eh SOC14 is currently processing or was last SOC converted
Fh SOC15 is currently processing or was last SOC converted

Reset type: SYSRSn

7ADCPWDNZR/W0hADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core.

0 All analog circuitry inside the core is powered down
1 All analog circuitry inside the core is powered up

Reset type: SYSRSn

6-3RESERVEDR0hReserved
2INTPULSEPOSR/W0hADC Interrupt Pulse Position.

0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register.
1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register

Reset type: SYSRSn

1-0RESERVEDR0hReserved

12.14.3.2 ADCCTL2 Register (Offset = 2h) [Reset = 00000000h]

ADCCTL2 is shown in Figure 12-40 and described in Table 12-41.

Return to the Summary Table.

ADC Control 2 Register

Figure 12-40 ADCCTL2 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVED
R-0hR-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDPRESCALE
R/W-0hR/W-0hR-0hR/W-0h
Table 12-41 ADCCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12-9RESERVEDR0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5-4RESERVEDR0hReserved
3-0PRESCALER/W0hADC Clock Prescaler.
0000 ADCCLK = Input Clock / 1.0
0001 ADCCLK = Input Clock / 1.5
0010 ADCCLK = Input Clock / 2.0
0011 ADCCLK = Input Clock / 2.5
0100 ADCCLK = Input Clock / 3.0
0101 ADCCLK = Input Clock / 3.5
0110 ADCCLK = Input Clock / 4.0
0111 ADCCLK = Input Clock / 4.5
1000 ADCCLK = Input Clock / 5.0
1001 ADCCLK = Input Clock / 5.5
1010 ADCCLK = Input Clock / 6.0
1011 ADCCLK = Input Clock / 6.5
1100 ADCCLK = Input Clock / 7.0
1101 ADCCLK = Input Clock / 7.5
1110 ADCCLK = Input Clock / 8.0
1111 ADCCLK = Input Clock / 8.5
Note: Non-integer ADC clock dividers are not recommended.

Reset type: SYSRSn

12.14.3.3 ADCINTSEL Register (Offset = 8h) [Reset = 00000000h]

ADCINTSEL is shown in Figure 12-41 and described in Table 12-42.

Return to the Summary Table.

ADC Interrupt 1, 2, 3 and 4 Selection Register

Figure 12-41 ADCINTSEL Register
3130292827262524
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
15141312111098
INT2EINT2CONTINT2SEL
R/W-0hR/W-0hR/W-0h
76543210
INT1EINT1CONTINT1SEL
R/W-0hR/W-0hR/W-0h
Table 12-42 ADCINTSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29-24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21-16RESERVEDR/W0hReserved
15INT2ER/W0hADCINT2 Interrupt Enable
0 ADCINT2 is disabled
1 ADCINT2 is enabled

Reset type: SYSRSn

14INT2CONTR/W0hADCINT2 Continue to Interrupt Mode
0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

13-8INT2SELR/W0hADCINT2 EOC Source Select
00h EOC0 is trigger for ADCINT2
01h EOC1 is trigger for ADCINT2
02h EOC2 is trigger for ADCINT2
03h EOC3 is trigger for ADCINT2
04h EOC4 is trigger for ADCINT2
05h EOC5 is trigger for ADCINT2
06h EOC6 is trigger for ADCINT2
07h EOC7 is trigger for ADCINT2
08h EOC8 is trigger for ADCINT2
09h EOC9 is trigger for ADCINT2
0Ah EOC10 is trigger for ADCINT2
0Bh EOC11 is trigger for ADCINT2
0Ch EOC12 is trigger for ADCINT2
0Dh EOC13 is trigger for ADCINT2
0Eh EOC14 is trigger for ADCINT2
0Fh EOC15 is trigger for ADCINT2
10h - 1Fh Reserved
20h OSINT1 is trigger for ADCINT2
21h - 3Fh Reserved

Reset type: SYSRSn

7INT1ER/W0hADCINT1 Interrupt Enable
0 ADCINT1 is disabled
1 ADCINT1 is enabled

Reset type: SYSRSn

6INT1CONTR/W0hADCINT1 Continue to Interrupt Mode
0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

5-0INT1SELR/W0hADCINT1 EOC Source Select
00h EOC0 is trigger for ADCINT1
01h EOC1 is trigger for ADCINT1
02h EOC2 is trigger for ADCINT1
03h EOC3 is trigger for ADCINT1
04h EOC4 is trigger for ADCINT1
05h EOC5 is trigger for ADCINT1
06h EOC6 is trigger for ADCINT1
07h EOC7 is trigger for ADCINT1
08h EOC8 is trigger for ADCINT1
09h EOC9 is trigger for ADCINT1
0Ah EOC10 is trigger for ADCINT1
0Bh EOC11 is trigger for ADCINT1
0Ch EOC12 is trigger for ADCINT1
0Dh EOC13 is trigger for ADCINT1
0Eh EOC14 is trigger for ADCINT1
0Fh EOC15 is trigger for ADCINT1
10h - 1Fh Reserved
20h OSINT1 is trigger for ADCINT1
21h - 3Fh Reserved

Reset type: SYSRSn

12.14.3.4 ADCDMAINTSEL Register (Offset = Ah) [Reset = 00000000h]

ADCDMAINTSEL is shown in Figure 12-42 and described in Table 12-43.

Return to the Summary Table.

ADC DMA Interrupt 1, 2, 3 and 4 Selection Register

Figure 12-42 ADCDMAINTSEL Register
3130292827262524
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
15141312111098
DMAINT2EDMAINT2CONTDMAINT2SEL
R/W-0hR/W-0hR/W-0h
76543210
DMAINT1EDMAINT1CONTDMAINT1SEL
R/W-0hR/W-0hR/W-0h
Table 12-43 ADCDMAINTSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29-24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21-16RESERVEDR/W0hReserved
15DMAINT2ER/W0hADCDMAINT2 Interrupt Enable
0 ADCDMAINT2 is disabled
1 ADCDMAINT2 is enabled

Reset type: SYSRSn

14DMAINT2CONTR/W0hADCDMAINT2 Continue to Interrupt Mode
0 No further ADCDMAINT2 pulses are generated until ADCDMAINT2 flag (in ADCDMAINTFLG register) is cleared by user.
1 ADCDMAINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

13-8DMAINT2SELR/W0hADCDMAINT2 EOC Source Select
00h EOC0 is trigger for ADCDMAINT2
01h EOC1 is trigger for ADCDMAINT2
02h EOC2 is trigger for ADCDMAINT2
03h EOC3 is trigger for ADCDMAINT2
04h EOC4 is trigger for ADCDMAINT2
05h EOC5 is trigger for ADCDMAINT2
06h EOC6 is trigger for ADCDMAINT2
07h EOC7 is trigger for ADCDMAINT2
08h EOC8 is trigger for ADCDMAINT2
09h EOC9 is trigger for ADCDMAINT2
0Ah EOC10 is trigger for ADCDMAINT2
0Bh EOC11 is trigger for ADCDMAINT2
0Ch EOC12 is trigger for ADCDMAINT2
0Dh EOC13 is trigger for ADCDMAINT2
0Eh EOC14 is trigger for ADCDMAINT2
0Fh EOC15 is trigger for ADCDMAINT2
10h - 1Fh Reserved
20h OSINT1 is trigger for ADCDMAINT2
21h - 3Fh Reserved

Reset type: SYSRSn

7DMAINT1ER/W0hADCDMAINT1 Interrupt Enable
0 ADCDMAINT1 is disabled
1 ADCDMAINT1 is enabled

Reset type: SYSRSn

6DMAINT1CONTR/W0hADCDMAINT1 Continue to Interrupt Mode
0 No further ADCDMAINT1 pulses are generated until ADCDMAINT1 flag (in ADCDMAINTFLG register) is cleared by user.
1 ADCDMAINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

5-0DMAINT1SELR/W0hADCDMAINT1 EOC Source Select
00h EOC0 is trigger for ADCDMAINT1
01h EOC1 is trigger for ADCDMAINT1
02h EOC2 is trigger for ADCDMAINT1
03h EOC3 is trigger for ADCDMAINT1
04h EOC4 is trigger for ADCDMAINT1
05h EOC5 is trigger for ADCDMAINT1
06h EOC6 is trigger for ADCDMAINT1
07h EOC7 is trigger for ADCDMAINT1
08h EOC8 is trigger for ADCDMAINT1
09h EOC9 is trigger for ADCDMAINT1
0Ah EOC10 is trigger for ADCDMAINT1
0Bh EOC11 is trigger for ADCDMAINT1
0Ch EOC12 is trigger for ADCDMAINT1
0Dh EOC13 is trigger for ADCDMAINT1
0Eh EOC14 is trigger for ADCDMAINT1
0Fh EOC15 is trigger for ADCDMAINT1
10h - 1Fh Reserved
20h OSINT1 is trigger for ADCDMAINT1
21h - 3Fh Reserved

Reset type: SYSRSn

12.14.3.5 ADCRAWINTFLG Register (Offset = Ch) [Reset = 00000000h]

ADCRAWINTFLG is shown in Figure 12-43 and described in Table 12-44.

Return to the Summary Table.

ADC Raw Interrupt Flag Register

Figure 12-43 ADCRAWINTFLG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMARAWINT2ADCDMARAWINT1
R-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDADCRAWINT2ADCRAWINT1
R-0hR-0hR-0hR-0hR-0h
Table 12-44 ADCRAWINTFLG Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17ADCDMARAWINT2R0hADC DMA Raw Interrupt 2 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting

0 Selected EOC/OSINT event did not occur
1 Selected EOC/OSINT event occurred

Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit.

Reset type: SYSRSn

16ADCDMARAWINT1R0hADC DMA Raw Interrupt 1 Flag. Reading these flags indicates if the associated ADCDMAINT condition occurred. This flag will be set irrespective of corresponding DMAINTE setting

0 Selected EOC/OSINT event did not occur
1 Selected EOC/OSINT event occurred

Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit.

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1ADCRAWINT2R0hADC RAW Interrupt 2 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting

0 Selected EOC/OSINT event did not occur
1 Selected EOC/OSINT event occured

Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit.

Reset type: SYSRSn

0ADCRAWINT1R0hADC RAW Interrupt 1 Flag. Reading these flags indicates if the associated INT condition occurred. This flag will be set irrespective of corresponding INTE setting

0 Selected EOC/OSINT event did not occur
1 Selected EOC/OSINT event occurred

Writing corresponding INTCLR bit in ADCINTFLGCLR register will clear this bit.

Reset type: SYSRSn

12.14.3.6 ADCINTFLG Register (Offset = Eh) [Reset = 00000000h]

ADCINTFLG is shown in Figure 12-44 and described in Table 12-45.

Return to the Summary Table.

ADC Interrupt Flag Register

Figure 12-44 ADCINTFLG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMAINT2ADCDMAINT1
R-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDRESERVEDADCINT2RESULTADCINT1RESULT
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRESERVEDRESERVEDADCINT2ADCINT1
R-0hR-0hR-0hR-0hR-0h
Table 12-45 ADCINTFLG Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17ADCDMAINT2R0hADC DMA Interrupt 2 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear.

0 No ADC DMA interrupt pulse generated
1 ADC DMA interrupt pulse generated

If the ADC DMA interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

16ADCDMAINT1R0hADC DMA Interrupt 1 Flag. Reading these flags indicates if the associated ADCDMAINT pulse was generated since the last clear.

0 No ADC DMA interrupt pulse generated
1 ADC DMA interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (DMAINTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

15-12RESERVEDR0hReserved
11RESERVEDR0hReserved
10RESERVEDR0hReserved
9ADCINT2RESULTR0hADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT2 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

8ADCINT1RESULTR0hADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT1 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

7-4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1ADCINT2R0hADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

0ADCINT1R0hADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSEL register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

12.14.3.7 ADCINTFLGFRC Register (Offset = 10h) [Reset = 00000000h]

ADCINTFLGFRC is shown in Figure 12-45 and described in Table 12-46.

Return to the Summary Table.

ADC Interrupt Flag Force Register

Figure 12-45 ADCINTFLGFRC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMAINT2ADCDMAINT1
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDADCINT2ADCINT1
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 12-46 ADCINTFLGFRC Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR-0/W1S0hReserved
18RESERVEDR-0/W1S0hReserved
17ADCDMAINT2R-0/W1S0hADC DMA interrupt 2 Flag Force. Reads return 0.

0 No action
1 Forces ADCDMAINT2 flags in the ADCINTFLG and ADCRAWINTFLG registers.

Reset type: SYSRSn

16ADCDMAINT1R-0/W1S0hADC DMA interrupt 1 Flag Force. Reads return 0.

0 No action
1 Forces ADCDMAINT1 flags in the ADCINTFLG and ADCRAWINTFLG registers.

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR-0/W1S0hReserved
2RESERVEDR-0/W1S0hReserved
1ADCINT2R-0/W1S0hADC Interrupt 2 Flag Force. Reads return 0.

0 No action
1 Forces ADCINT2 flags in the ADCINTFLG and ADCRAWINTFLG registers.

Reset type: SYSRSn

0ADCINT1R-0/W1S0hADC Interrupt 1 Flag Force. Reads return 0.

0 No action
1 Forces ADCINT1 flags in the ADCINTFLG and ADCRAWINTFLG registers.

Reset type: SYSRSn

12.14.3.8 ADCINTFLGCLR Register (Offset = 12h) [Reset = 00000000h]

ADCINTFLGCLR is shown in Figure 12-46 and described in Table 12-47.

Return to the Summary Table.

ADC Interrupt Flag Clear Register

Figure 12-46 ADCINTFLGCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMAINT2ADCDMAINT1
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDADCINT2ADCINT1
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 12-47 ADCINTFLGCLR Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR-0/W1C0hReserved
18RESERVEDR-0/W1C0hReserved
17ADCDMAINT2R-0/W1C0hADC DMA Interrupt 2 Flag Clear. Reads return 0.

0 No action
1 Clears ADDMACINT2 flags in the ADCINTFLG ,ADCRAWINTFLG registers.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

16ADCDMAINT1R-0/W1C0hADC DMA Interrupt 1 Flag Clear. Reads return 0.

0 No action
1 Clears ADDMACINT1 flags in the ADCINTFLG ,ADCRAWINTFLG registers.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR-0/W1C0hReserved
2RESERVEDR-0/W1C0hReserved
1ADCINT2R-0/W1C0hADC Interrupt 2 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG, ADCRAWINTFLG registers. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

0ADCINT1R-0/W1C0hADC Interrupt 1 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG, ADCRAWINTFLG registers.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

12.14.3.9 ADCINTOVF Register (Offset = 14h) [Reset = 00000000h]

ADCINTOVF is shown in Figure 12-47 and described in Table 12-48.

Return to the Summary Table.

ADC Interrupt Overflow Register

Figure 12-47 ADCINTOVF Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMAINT2OVFADCDMAINT1OVF
R-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDADCINT2OVFADCINT1OVF
R-0hR-0hR-0hR-0hR-0h
Table 12-48 ADCINTOVF Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17ADCDMAINT2OVFR0hADC DMA Interrupt 2 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC DMA Interrupt overflow event detected.
1 ADC DMA Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

16ADCDMAINT1OVFR0hADC DMA Interrupt 1 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC DMA Interrupt overflow event detected.
1 ADC DMA Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1ADCINT2OVFR0hADC Interrupt 2 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

0ADCINT1OVFR0hADC Interrupt 1 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

12.14.3.10 ADCINTOVFCLR Register (Offset = 16h) [Reset = 00000000h]

ADCINTOVFCLR is shown in Figure 12-48 and described in Table 12-49.

Return to the Summary Table.

ADC Interrupt Overflow Clear Register

Figure 12-48 ADCINTOVFCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESERVEDRESERVEDADCDMAINT2OVFADCDMAINT1OVF
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDADCINT2OVFADCINT1OVF
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 12-49 ADCINTOVFCLR Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19RESERVEDR-0/W1C0hReserved
18RESERVEDR-0/W1C0hReserved
17ADCDMAINT2OVFR-0/W1C0hADC DMA Interrupt 2 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

16ADCDMAINT1OVFR-0/W1C0hADC DMA Interrupt 1 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

15-4RESERVEDR0hReserved
3RESERVEDR-0/W1C0hReserved
2RESERVEDR-0/W1C0hReserved
1ADCINT2OVFR-0/W1C0hADC Interrupt 2 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

0ADCINT1OVFR-0/W1C0hADC Interrupt 1 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

12.14.3.11 ADCSOCPRICTL Register (Offset = 18h) [Reset = 00000400h]

ADCSOCPRICTL is shown in Figure 12-49 and described in Table 12-50.

Return to the Summary Table.

ADC SOC Priority Control Register

Figure 12-49 ADCSOCPRICTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRRPOINTER
R-0hR-10h
76543210
RRPOINTERRESERVEDSOCPRIORITY
R-10hR-0hR/W-0h
Table 12-50 ADCSOCPRICTL Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-6RRPOINTERR10hRound Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions.
00h SOC0 was last round robin SOC to convert, SOC1 is highest round robin priority.
01h SOC1 was last round robin SOC to convert, SOC2 is highest round robin priority.
02h SOC2 was last round robin SOC to convert, SOC3 is highest round robin priority.
03h SOC3 was last round robin SOC to convert, SOC4 is highest round robin priority.
04h SOC4 was last round robin SOC to convert, SOC5 is highest round robin priority.
05h SOC5 was last round robin SOC to convert, SOC6 is highest round robin priority.
06h SOC6 was last round robin SOC to convert, SOC7 is highest round robin priority.
07h SOC7 was last round robin SOC to convert, SOC8 is highest round robin priority.
08h SOC8 was last round robin SOC to convert, SOC9 is highest round robin priority.
09h SOC9 was last round robin SOC to convert, SOC10 is highest round robin priority.
0Ah SOC10 was last round robin SOC to convert, SOC11 is highest round robin priority.
0Bh SOC11 was last round robin SOC to convert, SOC12 is highest round robin priority.
0Ch SOC12 was last round robin SOC to convert, SOC13 is highest round robin priority.
0Dh SOC13 was last round robin SOC to convert, SOC14 is highest round robin priority.
0Eh SOC14 was last round robin SOC to convert, SOC15 is highest round robin priority.
0Fh SOC15 was last round robin SOC to convert, SOC0 is highest round robin priority.
10h Reset value to indicate no SOC has been converted. SOC0 is highest round robin priority. Set to this value when the ADC module is reset by SOFTPRES or when the ADCSOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect.
Others Invalid value.

Reset type: SYSRSn

5-2RESERVEDR0hReserved
1-0SOCPRIORITYR/W0hSOC Priority
Determines the cutoff point for priority mode and round robin arbitration for SOCx
0h SOC priority is handled in round robin mode for all channels.
1h SOC0 is high priority, rest of channels are in round robin mode.
2h SOC0-SOC1 are high priority, SOC2-SOC15 are in round robin mode.
3h SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin mode.

Reset type: SYSRSn

12.14.3.12 ADCINTSOCSEL1 Register (Offset = 1Ah) [Reset = 00000000h]

ADCINTSOCSEL1 is shown in Figure 12-50 and described in Table 12-51.

Return to the Summary Table.

ADC Interrupt SOC Selection 1 Register

Figure 12-50 ADCINTSOCSEL1 Register
31302928272625242322212019181716
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 12-51 ADCINTSOCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30SOC15R/W0hSOC15 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC15. TRIGSEL field alone determines SOC15 trigger.
01 ADCINT1 will trigger SOC15.
10 ADCINT2 will trigger SOC15.
11 EOC14 will trigger SOC15.

Reset type: SYSRSn

29-28SOC14R/W0hSOC14 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC14. TRIGSEL field alone determines SOC14 trigger.
01 ADCINT1 will trigger SOC14.
10 ADCINT2 will trigger SOC14.
11 EOC13 will trigger SOC14.

Reset type: SYSRSn

27-26SOC13R/W0hSOC13 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC13. TRIGSEL field alone determines SOC13 trigger.
01 ADCINT1 will trigger SOC13.
10 ADCINT2 will trigger SOC13.
11 EOC12 will trigger SOC13.

Reset type: SYSRSn

25-24SOC12R/W0hSOC12 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC12. TRIGSEL field alone determines SOC12 trigger.
01 ADCINT1 will trigger SOC12.
10 ADCINT2 will trigger SOC12.
11 EOC11 will trigger SOC12.

Reset type: SYSRSn

23-22SOC11R/W0hSOC11 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC11. TRIGSEL field alone determines SOC11 trigger.
01 ADCINT1 will trigger SOC11.
10 ADCINT2 will trigger SOC11.
11 EOC10 will trigger SOC11.

Reset type: SYSRSn

21-20SOC10R/W0hSOC10 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC10. TRIGSEL field alone determines SOC10 trigger.
01 ADCINT1 will trigger SOC10.
10 ADCINT2 will trigger SOC10.
11 EOC9 will trigger SOC10.

Reset type: SYSRSn

19-18SOC9R/W0hSOC9 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC9 trigger.
01 ADCINT1 will trigger SOC9.
10 ADCINT2 will trigger SOC1.
11 EOC8 will trigger SOC9.

Reset type: SYSRSn

17-16SOC8R/W0hSOC8 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC8 trigger.
01 ADCINT1 will trigger SOC8.
10 ADCINT2 will trigger SOC8.
11 EOC7 will trigger SOC8.

Reset type: SYSRSn

15-14SOC7R/W0hSOC7 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC7 trigger.
01 ADCINT1 will trigger SOC7.
10 ADCINT2 will trigger SOC7.
11 EOC6 will trigger SOC7.

Reset type: SYSRSn

13-12SOC6R/W0hSOC6 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC6 trigger.
01 ADCINT1 will trigger SOC6.
10 ADCINT2 will trigger SOC6.
11 EOC5 will trigger SOC6.

Reset type: SYSRSn

11-10SOC5R/W0hSOC5 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC5 trigger.
01 ADCINT1 will trigger SOC5.
10 ADCINT2 will trigger SOC5.
11 EOC4 will trigger SOC5.

Reset type: SYSRSn

9-8SOC4R/W0hSOC4 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC4 trigger.
01 ADCINT1 will trigger SOC4.
10 ADCINT2 will trigger SOC4.
11 EOC3 will trigger SOC4.

Reset type: SYSRSn

7-6SOC3R/W0hSOC3 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC3 trigger.
01 ADCINT1 will trigger SOC3.
10 ADCINT2 will trigger SOC3.
11 EOC2 will trigger SOC3.

Reset type: SYSRSn

5-4SOC2R/W0hSOC2 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC2 trigger.
01 ADCINT1 will trigger SOC2.
10 ADCINT2 will trigger SOC2.
11 EOC1 will trigger SOC2.

Reset type: SYSRSn

3-2SOC1R/W0hSOC1 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC1 trigger.
01 ADCINT1 will trigger SOC1.
10 ADCINT2 will trigger SOC1.
11 EOC0 will trigger SOC1.

Reset type: SYSRSn

1-0SOC0R/W0hSOC0 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC0.
10 ADCINT2 will trigger SOC0.
11 EOC[N-1] will trigger SOC0.
N - Total number of SOCs supported

Reset type: SYSRSn

12.14.3.13 ADCSOCFLG1 Register (Offset = 1Eh) [Reset = 00000000h]

ADCSOCFLG1 is shown in Figure 12-51 and described in Table 12-52.

Return to the Summary Table.

ADC SOC Flag 1 Register

Figure 12-51 ADCSOCFLG1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 12-52 ADCSOCFLG1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SOC15R0hSOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions.

0 No sample pending for SOC15.
1 Trigger has been received and sample is pending for SOC15.

This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

14SOC14R0hSOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions.

0 No sample pending for SOC14.
1 Trigger has been received and sample is pending for SOC14.

This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

13SOC13R0hSOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions.

0 No sample pending for SOC13.
1 Trigger has been received and sample is pending for SOC13.

This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

12SOC12R0hSOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions.

0 No sample pending for SOC12.
1 Trigger has been received and sample is pending for SOC12.

This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

11SOC11R0hSOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions.

0 No sample pending for SOC11.
1 Trigger has been received and sample is pending for SOC11.

This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

10SOC10R0hSOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions.

0 No sample pending for SOC10.
1 Trigger has been received and sample is pending for SOC10.

This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

9SOC9R0hSOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions.

0 No sample pending for SOC9.
1 Trigger has been received and sample is pending for SOC9.

This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

8SOC8R0hSOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions.

0 No sample pending for SOC8.
1 Trigger has been received and sample is pending for SOC8.

This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

7SOC7R0hSOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions.

0 No sample pending for SOC7.
1 Trigger has been received and sample is pending for SOC7.

This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

6SOC6R0hSOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions.

0 No sample pending for SOC6.
1 Trigger has been received and sample is pending for SOC6.

This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

5SOC5R0hSOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions.

0 No sample pending for SOC5.
1 Trigger has been received and sample is pending for SOC5.

This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

4SOC4R0hSOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions.

0 No sample pending for SOC4.
1 Trigger has been received and sample is pending for SOC4.

This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

3SOC3R0hSOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions.

0 No sample pending for SOC3.
1 Trigger has been received and sample is pending for SOC3.

This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

2SOC2R0hSOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions.

0 No sample pending for SOC2.
1 Trigger has been received and sample is pending for SOC2.

This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

1SOC1R0hSOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions.

0 No sample pending for SOC1.
1 Trigger has been received and sample is pending for SOC1.

This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

0SOC0R0hSOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions.

0 No sample pending for SOC0.
1 Trigger has been received and sample is pending for SOC0.

This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

12.14.3.14 ADCSOCFRC1 Register (Offset = 20h) [Reset = 00000000h]

ADCSOCFRC1 is shown in Figure 12-52 and described in Table 12-53.

Return to the Summary Table.

ADC SOC Force 1 Register

Figure 12-52 ADCSOCFRC1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 12-53 ADCSOCFRC1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SOC15R-0/W1S0hSOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC15 flag bit to 1. This will cause a conversion to start once priority is given to SOC15.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC15 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

14SOC14R-0/W1S0hSOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC14 flag bit to 1. This will cause a conversion to start once priority is given to SOC14.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC14 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

13SOC13R-0/W1S0hSOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC13 flag bit to 1. This will cause a conversion to start once priority is given to SOC13.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC13 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

12SOC12R-0/W1S0hSOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC12 flag bit to 1. This will cause a conversion to start once priority is given to SOC12.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC12 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

11SOC11R-0/W1S0hSOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC11 flag bit to 1. This will cause a conversion to start once priority is given to SOC11.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC11 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

10SOC10R-0/W1S0hSOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC10 flag bit to 1. This will cause a conversion to start once priority is given to SOC10.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC10 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

9SOC9R-0/W1S0hSOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC9 flag bit to 1. This will cause a conversion to start once priority is given to SOC9.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC9 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

8SOC8R-0/W1S0hSOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC8 flag bit to 1. This will cause a conversion to start once priority is given to SOC8.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC8 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

7SOC7R-0/W1S0hSOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC7 flag bit to 1. This will cause a conversion to start once priority is given to SOC7.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC7 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

6SOC6R-0/W1S0hSOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC6 flag bit to 1. This will cause a conversion to start once priority is given to SOC6.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC6 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

5SOC5R-0/W1S0hSOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC5 flag bit to 1. This will cause a conversion to start once priority is given to SOC5.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC5 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

4SOC4R-0/W1S0hSOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC4 flag bit to 1. This will cause a conversion to start once priority is given to SOC4.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC4 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

3SOC3R-0/W1S0hSOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC3 flag bit to 1. This will cause a conversion to start once priority is given to SOC3.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC3 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

2SOC2R-0/W1S0hSOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC2 flag bit to 1. This will cause a conversion to start once priority is given to SOC2.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC2 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

1SOC1R-0/W1S0hSOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC1 flag bit to 1. This will cause a conversion to start once priority is given to SOC1.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC1 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

0SOC0R-0/W1S0hSOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC0 flag bit to 1. This will cause a conversion to start once priority is given to SOC0.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC0 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

12.14.3.15 ADCSOCOVF1 Register (Offset = 22h) [Reset = 00000000h]

ADCSOCOVF1 is shown in Figure 12-53 and described in Table 12-54.

Return to the Summary Table.

ADC SOC Overflow 1 Register

Figure 12-53 ADCSOCOVF1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
SOC15OVFSOC14OVFSOC13OVFSOC12OVFSOC11OVFSOC10OVFSOC9OVFSOC8OVF
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SOC7OVFSOC6OVFSOC5OVFSOC4OVFSOC3OVFSOC2OVFSOC1OVFSOC0OVF
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 12-54 ADCSOCOVF1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SOC15OVFR0hSOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending.

0 No SOC15 event overflow.
1 SOC15 event overflow.

An overflow condition does not stop SOC15 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

14SOC14OVFR0hSOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending.

0 No SOC14 event overflow.
1 SOC14 event overflow.

An overflow condition does not stop SOC14 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

13SOC13OVFR0hSOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending.

0 No SOC13 event overflow.
1 SOC13 event overflow.

An overflow condition does not stop SOC13 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

12SOC12OVFR0hSOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending.

0 No SOC12 event overflow.
1 SOC12 event overflow.

An overflow condition does not stop SOC12 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

11SOC11OVFR0hSOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending.

0 No SOC11 event overflow.
1 SOC11 event overflow.

An overflow condition does not stop SOC11 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

10SOC10OVFR0hSOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending.

0 No SOC10 event overflow.
1 SOC10 event overflow.

An overflow condition does not stop SOC10 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

9SOC9OVFR0hSOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending.

0 No SOC9 event overflow.
1 SOC9 event overflow.

An overflow condition does not stop SOC9 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

8SOC8OVFR0hSOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending.

0 No SOC8 event overflow.
1 SOC8 event overflow.

An overflow condition does not stop SOC8 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

7SOC7OVFR0hSOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending.

0 No SOC7 event overflow.
1 SOC7 event overflow.

An overflow condition does not stop SOC7 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

6SOC6OVFR0hSOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending.

0 No SOC6 event overflow.
1 SOC6 event overflow.

An overflow condition does not stop SOC6 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

5SOC5OVFR0hSOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending.

0 No SOC5 event overflow.
1 SOC5 event overflow.

An overflow condition does not stop SOC5 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

4SOC4OVFR0hSOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending.

0 No SOC4 event overflow.
1 SOC4 event overflow.

An overflow condition does not stop SOC4 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

3SOC3OVFR0hSOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending.

0 No SOC3 event overflow.
1 SOC3 event overflow.

An overflow condition does not stop SOC3 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

2SOC2OVFR0hSOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending.

0 No SOC2 event overflow.
1 SOC2 event overflow.

An overflow condition does not stop SOC2 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

1SOC1OVFR0hSOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending.

0 No SOC1 event overflow.
1 SOC1 event overflow.

An overflow condition does not stop SOC1 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

0SOC0OVFR0hSOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending.

0 No SOC0 event overflow.
1 SOC0 event overflow.

An overflow condition does not stop SOC0 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

12.14.3.16 ADCSOCOVFCLR1 Register (Offset = 24h) [Reset = 00000000h]

ADCSOCOVFCLR1 is shown in Figure 12-54 and described in Table 12-55.

Return to the Summary Table.

ADC SOC Overflow Clear 1 Register

Figure 12-54 ADCSOCOVFCLR1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
SOC15OVFSOC14OVFSOC13OVFSOC12OVFSOC11OVFSOC10OVFSOC9OVFSOC8OVF
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
SOC7OVFSOC6OVFSOC5OVFSOC4OVFSOC3OVFSOC2OVFSOC1OVFSOC0OVF
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 12-55 ADCSOCOVFCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SOC15OVFR-0/W1C0hSOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC15 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

14SOC14OVFR-0/W1C0hSOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC14 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

13SOC13OVFR-0/W1C0hSOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC13 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

12SOC12OVFR-0/W1C0hSOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC12 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

11SOC11OVFR-0/W1C0hSOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC11 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

10SOC10OVFR-0/W1C0hSOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC10 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

9SOC9OVFR-0/W1C0hSOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC9 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

8SOC8OVFR-0/W1C0hSOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC8 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

7SOC7OVFR-0/W1C0hSOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC7 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

6SOC6OVFR-0/W1C0hSOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC6 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

5SOC5OVFR-0/W1C0hSOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC5 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

4SOC4OVFR-0/W1C0hSOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC4 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

3SOC3OVFR-0/W1C0hSOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC3 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

2SOC2OVFR-0/W1C0hSOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC2 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

1SOC1OVFR-0/W1C0hSOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC1 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

0SOC0OVFR-0/W1C0hSOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC0 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

12.14.3.17 ADCSOC0CTL Register (Offset = 26h) [Reset = 00000200h]

ADCSOC0CTL is shown in Figure 12-55 and described in Table 12-56.

Return to the Summary Table.

ADC SOC0 Control Register

Figure 12-55 ADCSOC0CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-56 ADCSOC0CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC0 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC0 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.18 ADCSOC1CTL Register (Offset = 28h) [Reset = 00000200h]

ADCSOC1CTL is shown in Figure 12-56 and described in Table 12-57.

Return to the Summary Table.

ADC SOC1 Control Register

Figure 12-56 ADCSOC1CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-57 ADCSOC1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC1 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC1 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.19 ADCSOC2CTL Register (Offset = 2Ah) [Reset = 00000200h]

ADCSOC2CTL is shown in Figure 12-57 and described in Table 12-58.

Return to the Summary Table.

ADC SOC2 Control Register

Figure 12-57 ADCSOC2CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-58 ADCSOC2CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC2 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC2 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.20 ADCSOC3CTL Register (Offset = 2Ch) [Reset = 00000200h]

ADCSOC3CTL is shown in Figure 12-58 and described in Table 12-59.

Return to the Summary Table.

ADC SOC3 Control Register

Figure 12-58 ADCSOC3CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-59 ADCSOC3CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC3 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC3 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.21 ADCSOC4CTL Register (Offset = 2Eh) [Reset = 00000200h]

ADCSOC4CTL is shown in Figure 12-59 and described in Table 12-60.

Return to the Summary Table.

ADC SOC4 Control Register

Figure 12-59 ADCSOC4CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-60 ADCSOC4CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC4 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC4 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.22 ADCSOC5CTL Register (Offset = 30h) [Reset = 00000200h]

ADCSOC5CTL is shown in Figure 12-60 and described in Table 12-61.

Return to the Summary Table.

ADC SOC5 Control Register

Figure 12-60 ADCSOC5CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-61 ADCSOC5CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC5 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC5 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.23 ADCSOC6CTL Register (Offset = 32h) [Reset = 00000200h]

ADCSOC6CTL is shown in Figure 12-61 and described in Table 12-62.

Return to the Summary Table.

ADC SOC6 Control Register

Figure 12-61 ADCSOC6CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-62 ADCSOC6CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC6 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC6 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.24 ADCSOC7CTL Register (Offset = 34h) [Reset = 00000200h]

ADCSOC7CTL is shown in Figure 12-62 and described in Table 12-63.

Return to the Summary Table.

ADC SOC7 Control Register

Figure 12-62 ADCSOC7CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-63 ADCSOC7CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC7 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC7 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.25 ADCSOC8CTL Register (Offset = 36h) [Reset = 00000200h]

ADCSOC8CTL is shown in Figure 12-63 and described in Table 12-64.

Return to the Summary Table.

ADC SOC8 Control Register

Figure 12-63 ADCSOC8CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-64 ADCSOC8CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC8 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC8 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.26 ADCSOC9CTL Register (Offset = 38h) [Reset = 00000200h]

ADCSOC9CTL is shown in Figure 12-64 and described in Table 12-65.

Return to the Summary Table.

ADC SOC9 Control Register

Figure 12-64 ADCSOC9CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-65 ADCSOC9CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC9 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC9 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.27 ADCSOC10CTL Register (Offset = 3Ah) [Reset = 00000200h]

ADCSOC10CTL is shown in Figure 12-65 and described in Table 12-66.

Return to the Summary Table.

ADC SOC10 Control Register

Figure 12-65 ADCSOC10CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-66 ADCSOC10CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC10 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC10 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.28 ADCSOC11CTL Register (Offset = 3Ch) [Reset = 00000200h]

ADCSOC11CTL is shown in Figure 12-66 and described in Table 12-67.

Return to the Summary Table.

ADC SOC11 Control Register

Figure 12-66 ADCSOC11CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-67 ADCSOC11CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC11 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC11 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.29 ADCSOC12CTL Register (Offset = 3Eh) [Reset = 00000200h]

ADCSOC12CTL is shown in Figure 12-67 and described in Table 12-68.

Return to the Summary Table.

ADC SOC12 Control Register

Figure 12-67 ADCSOC12CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-68 ADCSOC12CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC12 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC12 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.30 ADCSOC13CTL Register (Offset = 40h) [Reset = 00000200h]

ADCSOC13CTL is shown in Figure 12-68 and described in Table 12-69.

Return to the Summary Table.

ADC SOC13 Control Register

Figure 12-68 ADCSOC13CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-69 ADCSOC13CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC13 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC13 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.31 ADCSOC14CTL Register (Offset = 42h) [Reset = 00000200h]

ADCSOC14CTL is shown in Figure 12-69 and described in Table 12-70.

Return to the Summary Table.

ADC SOC14 Control Register

Figure 12-69 ADCSOC14CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-70 ADCSOC14CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC14 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC14 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.32 ADCSOC15CTL Register (Offset = 44h) [Reset = 00000200h]

ADCSOC15CTL is shown in Figure 12-70 and described in Table 12-71.

Return to the Summary Table.

ADC SOC15 Control Register

Figure 12-70 ADCSOC15CTL Register
3130292827262524
RESERVEDTRIGSEL
R-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDSAMPCAPRESETSELSAMPCAPRESETDISABLERESERVED
R/W-0hR-0hR/W-0hR/W-1hR-0h
76543210
ACQPS
R/W-0h
Table 12-71 ADCSOC15CTL Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-20TRIGSELR/W0hSOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h ADCTRIG0 - Software only
01h - 1Fh Hardware triggers

Reset type: SYSRSn

19-15CHSELR/W0hSOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC.
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Reset type: SYSRSn

14-11RESERVEDR0hReserved
10SAMPCAPRESETSELR/W0hSOC15 Sample Cap Reset Select : Resets sample cap after conversion to either VREFHI/2 or VREFLO
0 - The sample cap is reset to VREFLO after each conversion
1 - The sample cap is reset to VREFHI/2 after each conversion

Reset type: SYSRSn

9SAMPCAPRESETDISABLER/W1hSOC15 Sample Cap Reset enable : Resets sample cap after conversion.
0 - The sample cap is reset after each conversion
1 - The sample cap is not reset after each conversion

Reset type: SYSRSn

8RESERVEDR0hReserved
7-0ACQPSR/W0hSOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold window duration.
S+H window values is defined based on a combonation of ACQPS[7:6] and ACQPS[5:0] values
If ACQPS[7:6] value is
'00' S+H window = ACQPS[5:0] + 1 sysclk cycles
'01' S+H window = 64 + ((ACQPS[5:0] +1) * 2) sysclk cycles
'10' S+H window = 192 + ((ACQPS[5:0] +1) * 4) sysclk cycles
'11' S+H window = 448 + ((ACQPS[5:0] +1) * 16) sysclk cycles

Reset type: SYSRSn

12.14.3.33 ADCEVTSTAT Register (Offset = 66h) [Reset = 00000000h]

ADCEVTSTAT is shown in Figure 12-71 and described in Table 12-72.

Return to the Summary Table.

ADC Event Status Register

Figure 12-71 ADCEVTSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDPPB3INLIMITPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
PPB2INLIMITPPB2ZEROPPB2TRIPLOPPB2TRIPHIPPB1INLIMITPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 12-72 ADCEVTSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR0hReserved
14RESERVEDR0hReserved
13RESERVEDR0hReserved
12RESERVEDR0hReserved
11PPB3INLIMITR0hPost Processing Block 3 In-Limit Trip Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

10PPB3ZEROR0hPost Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

9PPB3TRIPLOR0hPost Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

8PPB3TRIPHIR0hPost Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

7PPB2INLIMITR0hPost Processing Block 2 In-Limit Trip Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

6PPB2ZEROR0hPost Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

5PPB2TRIPLOR0hPost Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

4PPB2TRIPHIR0hPost Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

3PPB1INLIMITR0hPost Processing Block 1 In-Limit Trip Flag. When set indicates a digital compare within limit event has occurred. This will be set when the PPB result is either in between or equal to the TRIPHI and TRIPLO thresholds.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

2PPB1ZEROR0hPost Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

1PPB1TRIPLOR0hPost Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

0PPB1TRIPHIR0hPost Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

12.14.3.34 ADCEVTCLR Register (Offset = 68h) [Reset = 00000000h]

ADCEVTCLR is shown in Figure 12-72 and described in Table 12-73.

Return to the Summary Table.

ADC Event Clear Register

Figure 12-72 ADCEVTCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDPPB3INLIMITPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
76543210
PPB2INLIMITPPB2ZEROPPB2TRIPLOPPB2TRIPHIPPB1INLIMITPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 12-73 ADCEVTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR-0/W1C0hReserved
14RESERVEDR-0/W1C0hReserved
13RESERVEDR-0/W1C0hReserved
12RESERVEDR-0/W1C0hReserved
11PPB3INLIMITR-0/W1C0hPost Processing Block 3 In-Limit Trip Flag Clear. Clears the corresponding within trip limit flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

10PPB3ZEROR-0/W1C0hPost Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

9PPB3TRIPLOR-0/W1C0hPost Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

8PPB3TRIPHIR-0/W1C0hPost Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

7PPB2INLIMITR-0/W1C0hPost Processing Block 2 In-Limit Trip Flag Clear. Clears the corresponding within trip limit flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

6PPB2ZEROR-0/W1C0hPost Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

5PPB2TRIPLOR-0/W1C0hPost Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

4PPB2TRIPHIR-0/W1C0hPost Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

3PPB1INLIMITR-0/W1C0hPost Processing Block 1 In-Limit Trip Flag Clear. Clears the corresponding within trip limit flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

2PPB1ZEROR-0/W1C0hPost Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

1PPB1TRIPLOR-0/W1C0hPost Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

0PPB1TRIPHIR-0/W1C0hPost Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

12.14.3.35 ADCEVTSEL Register (Offset = 6Ah) [Reset = 00000000h]

ADCEVTSEL is shown in Figure 12-73 and described in Table 12-74.

Return to the Summary Table.

ADC Event Selection Register

Figure 12-73 ADCEVTSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDPPB3INLIMITPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
PPB2INLIMITPPB2ZEROPPB2TRIPLOPPB2TRIPHIPPB1INLIMITPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 12-74 ADCEVTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11PPB3INLIMITR/W0hPost Processing Block 3 In-Limit Trip Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

10PPB3ZEROR/W0hPost Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

9PPB3TRIPLOR/W0hPost Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

8PPB3TRIPHIR/W0hPost Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

7PPB2INLIMITR/W0hPost Processing Block 2 In-Limit Trip Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

6PPB2ZEROR/W0hPost Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

5PPB2TRIPLOR/W0hPost Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

4PPB2TRIPHIR/W0hPost Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

3PPB1INLIMITR/W0hPost Processing Block 1 In-Limit Trip Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

2PPB1ZEROR/W0hPost Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

1PPB1TRIPLOR/W0hPost Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

0PPB1TRIPHIR/W0hPost Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

12.14.3.36 ADCEVTINTSEL Register (Offset = 6Ch) [Reset = 00000000h]

ADCEVTINTSEL is shown in Figure 12-74 and described in Table 12-75.

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ADC Event Interrupt Selection Register

Figure 12-74 ADCEVTINTSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDPPB3INLIMITPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
PPB2INLIMITPPB2ZEROPPB2TRIPLOPPB2TRIPHIPPB1INLIMITPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 12-75 ADCEVTINTSEL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11PPB3INLIMITR/W0hPost Processing Block 3 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

10PPB3ZEROR/W0hPost Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

9PPB3TRIPLOR/W0hPost Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

8PPB3TRIPHIR/W0hPost Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

7PPB2INLIMITR/W0hPost Processing Block 2 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

6PPB2ZEROR/W0hPost Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

5PPB2TRIPLOR/W0hPost Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

4PPB2TRIPHIR/W0hPost Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

3PPB1INLIMITR/W0hPost Processing Block 1 Within trip limit Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

2PPB1ZEROR/W0hPost Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

1PPB1TRIPLOR/W0hPost Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

0PPB1TRIPHIR/W0hPost Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

12.14.3.37 ADCREV Register (Offset = 72h) [Reset = 00000006h]

ADCREV is shown in Figure 12-75 and described in Table 12-76.

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ADC Revision Register

Figure 12-75 ADCREV Register
313029282726252423222120191817161514131211109876543210
REVTYPE
R-0hR-6h
Table 12-76 ADCREV Register Field Descriptions
BitFieldTypeResetDescription
31-8REVR0hADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h.

Reset type: SYSRSn

7-0TYPER6hADC Type. Always set to 6 for this HSADC-12b.

Reset type: SYSRSn

12.14.3.38 ADCOFFTRIM Register (Offset = 74h) [Reset = 00000000h]

ADCOFFTRIM is shown in Figure 12-76 and described in Table 12-77.

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ADC Offset Trim Register 1

Figure 12-76 ADCOFFTRIM Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFTRIM
R-0hR/W-0h
Table 12-77 ADCOFFTRIM Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0OFFTRIMR/W0hADC Offset Trim

Adjusts the conversion results of the converter up
or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot.

Offset can be corrected in the range of +7 to -8 LSBs. Value is 16*Offset in 8-bit 2's complement:

7 LSB (16*7) = 112
6 LSB (16*6) = 96
5 LSB (16*5) = 80
4 LSB (16*4) = 64
3 LSB (16*3) = 48
2 LSB (16*2) = 32
1 LSB (16*1) = 16
0 LSB (16*0) = 0
-1 LSB (16*(-1)) = 240
:
:
-7LSB(16*(-7)) = 144

Reset type: XRSn

12.14.3.39 ADCPPB1CONFIG Register (Offset = 80h) [Reset = 00000000h]

ADCPPB1CONFIG is shown in Figure 12-77 and described in Table 12-78.

Return to the Summary Table.

ADC PPB{#} Config Register

Figure 12-77 ADCPPB1CONFIG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
TWOSCOMPENRESERVEDCBCENRESERVEDCONFIG
R/W-0hR-0hR/W-0hR-0hR/W-0h
Table 12-78 ADCPPB1CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7TWOSCOMPENR/W0hADC Post Processing Block {#} Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB{#}RESULT register.

0 ADCPPB{#}RESULT = ADCRESULTx - ADCPPB{#}OFFREF
1 ADCPPB{#}RESULT = ADCPPB{#}OFFREF - ADCRESULTx

Reset type: SYSRSn

6RESERVEDR0hReserved
5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4RESERVEDR0hReserved
3-0CONFIGR/W0hADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block.

0000 SOC0/EOC0/RESULT0 is associated with post processing block {#}
0001 SOC1/EOC1/RESULT1 is associated with post processing block {#}
0010 SOC2/EOC2/RESULT2 is associated with post processing block {#}
0011 SOC3/EOC3/RESULT3 is associated with post processing block {#}
0100 SOC4/EOC4/RESULT4 is associated with post processing block {#}
0101 SOC5/EOC5/RESULT5 is associated with post processing block {#}
0110 SOC6/EOC6/RESULT6 is associated with post processing block {#}
0111 SOC7/EOC7/RESULT7 is associated with post processing block {#}
1000 SOC8/EOC8/RESULT8 is associated with post processing block {#}
1001 SOC9/EOC9/RESULT9 is associated with post processing block {#}
1010 SOC10/EOC10/RESULT10 is associated with post processing block {#}
1011 SOC11/EOC11/RESULT11 is associated with post processing block {#}
1100 SOC12/EOC12/RESULT12 is associated with post processing block {#}
1101 SOC13/EOC13/RESULT13 is associated with post processing block {#}
1110 SOC14/EOC14/RESULT14 is associated with post processing block {#}
1111 SOC15/EOC15/RESULT15 is associated with post processing block {#}

Reset type: SYSRSn

12.14.3.40 ADCPPB1OFFCAL Register (Offset = 84h) [Reset = 00000000h]

ADCPPB1OFFCAL is shown in Figure 12-78 and described in Table 12-79.

Return to the Summary Table.

ADC PPB1 Offset Calibration Register

Figure 12-78 ADCPPB1OFFCAL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFCAL
R-0hR/W-0h
Table 12-79 ADCPPB1OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0OFFCALR/W0hADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 6-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

00h No change. The ADC output is stored directly into ADCRESULT.
01h ADC output - 1 is stored into ADCRESULT.
02h ADC output - 2 is stored into ADCRESULT.
...
20h ADC output + 32 is stored into ADCRESULT.
...
3Fh ADC output + 1 is stored into ADCRESULT.

NOTE: The subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

12.14.3.41 ADCPPB1OFFREF Register (Offset = 86h) [Reset = 00000000h]

ADCPPB1OFFREF is shown in Figure 12-79 and described in Table 12-80.

Return to the Summary Table.

ADC PPB1 Offset Reference Register

Figure 12-79 ADCPPB1OFFREF Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFREF
R-0hR/W-0h
Table 12-80 ADCPPB1OFFREF Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0OFFREFR/W0hADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 12-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB1RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
001h ADCRESULT - 1 is passed on.
002h ADCRESULT - 2 is passed on.
...
800h ADCRESULT - 2048 is passed on.
...
FFFh ADCRESULT - 4096 is passed on.

Reset type: SYSRSn

12.14.3.42 ADCPPB1TRIPHI Register (Offset = 88h) [Reset = 00000000h]

ADCPPB1TRIPHI is shown in Figure 12-80 and described in Table 12-81.

Return to the Summary Table.

ADC PPB1 Trip High Register

Figure 12-80 ADCPPB1TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 12-81 ADCPPB1TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITHIR/W0hADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[15:13] will be ignored

Reset type: SYSRSn

12.14.3.43 ADCPPB1TRIPLO Register (Offset = 8Ah) [Reset = 00000000h]

ADCPPB1TRIPLO is shown in Figure 12-81 and described in Table 12-82.

Return to the Summary Table.

ADC PPB1 Trip Low/Trigger Time Stamp Register

Figure 12-81 ADCPPB1TRIPLO Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 12-82 ADCPPB1TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITLOR/W0hADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO[15:13] will be ignored in 12 bit mode

Reset type: SYSRSn

12.14.3.44 ADCPPB2CONFIG Register (Offset = 90h) [Reset = 00000001h]

ADCPPB2CONFIG is shown in Figure 12-82 and described in Table 12-83.

Return to the Summary Table.

ADC PPB{#} Config Register

Figure 12-82 ADCPPB2CONFIG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
TWOSCOMPENRESERVEDCBCENRESERVEDCONFIG
R/W-0hR-0hR/W-0hR-0hR/W-1h
Table 12-83 ADCPPB2CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7TWOSCOMPENR/W0hADC Post Processing Block {#} Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB{#}RESULT register.

0 ADCPPB{#}RESULT = ADCRESULTx - ADCPPB{#}OFFREF
1 ADCPPB{#}RESULT = ADCPPB{#}OFFREF - ADCRESULTx

Reset type: SYSRSn

6RESERVEDR0hReserved
5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4RESERVEDR0hReserved
3-0CONFIGR/W1hADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block.

0000 SOC0/EOC0/RESULT0 is associated with post processing block {#}
0001 SOC1/EOC1/RESULT1 is associated with post processing block {#}
0010 SOC2/EOC2/RESULT2 is associated with post processing block {#}
0011 SOC3/EOC3/RESULT3 is associated with post processing block {#}
0100 SOC4/EOC4/RESULT4 is associated with post processing block {#}
0101 SOC5/EOC5/RESULT5 is associated with post processing block {#}
0110 SOC6/EOC6/RESULT6 is associated with post processing block {#}
0111 SOC7/EOC7/RESULT7 is associated with post processing block {#}
1000 SOC8/EOC8/RESULT8 is associated with post processing block {#}
1001 SOC9/EOC9/RESULT9 is associated with post processing block {#}
1010 SOC10/EOC10/RESULT10 is associated with post processing block {#}
1011 SOC11/EOC11/RESULT11 is associated with post processing block {#}
1100 SOC12/EOC12/RESULT12 is associated with post processing block {#}
1101 SOC13/EOC13/RESULT13 is associated with post processing block {#}
1110 SOC14/EOC14/RESULT14 is associated with post processing block {#}
1111 SOC15/EOC15/RESULT15 is associated with post processing block {#}

Reset type: SYSRSn

12.14.3.45 ADCPPB2OFFCAL Register (Offset = 94h) [Reset = 00000000h]

ADCPPB2OFFCAL is shown in Figure 12-83 and described in Table 12-84.

Return to the Summary Table.

ADC PPB2 Offset Calibration Register

Figure 12-83 ADCPPB2OFFCAL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFCAL
R-0hR/W-0h
Table 12-84 ADCPPB2OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0OFFCALR/W0hADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 6-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

00h No change. The ADC output is stored directly into ADCRESULT.
01h ADC output - 1 is stored into ADCRESULT.
02h ADC output - 2 is stored into ADCRESULT.
...
20h ADC output + 32 is stored into ADCRESULT.
...
3Fh ADC output + 1 is stored into ADCRESULT.

NOTE: The subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

12.14.3.46 ADCPPB2OFFREF Register (Offset = 96h) [Reset = 00000000h]

ADCPPB2OFFREF is shown in Figure 12-84 and described in Table 12-85.

Return to the Summary Table.

ADC PPB2 Offset Reference Register

Figure 12-84 ADCPPB2OFFREF Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFREF
R-0hR/W-0h
Table 12-85 ADCPPB2OFFREF Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0OFFREFR/W0hADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 12-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB2RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
001h ADCRESULT - 1 is passed on.
002h ADCRESULT - 2 is passed on.
...
800h ADCRESULT - 2048 is passed on.
...
FFFh ADCRESULT - 4096 is passed on.

Reset type: SYSRSn

12.14.3.47 ADCPPB2TRIPHI Register (Offset = 98h) [Reset = 00000000h]

ADCPPB2TRIPHI is shown in Figure 12-85 and described in Table 12-86.

Return to the Summary Table.

ADC PPB2 Trip High Register

Figure 12-85 ADCPPB2TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 12-86 ADCPPB2TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITHIR/W0hADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[15:13] will be ignored

Reset type: SYSRSn

12.14.3.48 ADCPPB2TRIPLO Register (Offset = 9Ah) [Reset = 00000000h]

ADCPPB2TRIPLO is shown in Figure 12-86 and described in Table 12-87.

Return to the Summary Table.

ADC PPB2 Trip Low/Trigger Time Stamp Register

Figure 12-86 ADCPPB2TRIPLO Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 12-87 ADCPPB2TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITLOR/W0hADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO[15:13] will be ignored in 12 bit mode

Reset type: SYSRSn

12.14.3.49 ADCPPB3CONFIG Register (Offset = A0h) [Reset = 00000002h]

ADCPPB3CONFIG is shown in Figure 12-87 and described in Table 12-88.

Return to the Summary Table.

ADC PPB{#} Config Register

Figure 12-87 ADCPPB3CONFIG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
TWOSCOMPENRESERVEDCBCENRESERVEDCONFIG
R/W-0hR-0hR/W-0hR-0hR/W-2h
Table 12-88 ADCPPB3CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7TWOSCOMPENR/W0hADC Post Processing Block {#} Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB{#}RESULT register.

0 ADCPPB{#}RESULT = ADCRESULTx - ADCPPB{#}OFFREF
1 ADCPPB{#}RESULT = ADCPPB{#}OFFREF - ADCRESULTx

Reset type: SYSRSn

6RESERVEDR0hReserved
5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4RESERVEDR0hReserved
3-0CONFIGR/W2hADC Post Processing Block {#} Configuration. This bit field defines which SOC/EOC/RESULT is associated with this post processing block.

0000 SOC0/EOC0/RESULT0 is associated with post processing block {#}
0001 SOC1/EOC1/RESULT1 is associated with post processing block {#}
0010 SOC2/EOC2/RESULT2 is associated with post processing block {#}
0011 SOC3/EOC3/RESULT3 is associated with post processing block {#}
0100 SOC4/EOC4/RESULT4 is associated with post processing block {#}
0101 SOC5/EOC5/RESULT5 is associated with post processing block {#}
0110 SOC6/EOC6/RESULT6 is associated with post processing block {#}
0111 SOC7/EOC7/RESULT7 is associated with post processing block {#}
1000 SOC8/EOC8/RESULT8 is associated with post processing block {#}
1001 SOC9/EOC9/RESULT9 is associated with post processing block {#}
1010 SOC10/EOC10/RESULT10 is associated with post processing block {#}
1011 SOC11/EOC11/RESULT11 is associated with post processing block {#}
1100 SOC12/EOC12/RESULT12 is associated with post processing block {#}
1101 SOC13/EOC13/RESULT13 is associated with post processing block {#}
1110 SOC14/EOC14/RESULT14 is associated with post processing block {#}
1111 SOC15/EOC15/RESULT15 is associated with post processing block {#}

Reset type: SYSRSn

12.14.3.50 ADCPPB3OFFCAL Register (Offset = A4h) [Reset = 00000000h]

ADCPPB3OFFCAL is shown in Figure 12-88 and described in Table 12-89.

Return to the Summary Table.

ADC PPB3 Offset Calibration Register

Figure 12-88 ADCPPB3OFFCAL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFCAL
R-0hR/W-0h
Table 12-89 ADCPPB3OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0OFFCALR/W0hADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 6-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

00h No change. The ADC output is stored directly into ADCRESULT.
01h ADC output - 1 is stored into ADCRESULT.
02h ADC output - 2 is stored into ADCRESULT.
...
20h ADC output + 32 is stored into ADCRESULT.
...
3Fh ADC output + 1 is stored into ADCRESULT.

NOTE: The subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

12.14.3.51 ADCPPB3OFFREF Register (Offset = A6h) [Reset = 00000000h]

ADCPPB3OFFREF is shown in Figure 12-89 and described in Table 12-90.

Return to the Summary Table.

ADC PPB3 Offset Reference Register

Figure 12-89 ADCPPB3OFFREF Register
313029282726252423222120191817161514131211109876543210
RESERVEDOFFREF
R-0hR/W-0h
Table 12-90 ADCPPB3OFFREF Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0OFFREFR/W0hADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 12-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB3RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
001h ADCRESULT - 1 is passed on.
002h ADCRESULT - 2 is passed on.
...
800h ADCRESULT - 2048 is passed on.
...
FFFh ADCRESULT - 4096 is passed on.

Reset type: SYSRSn

12.14.3.52 ADCPPB3TRIPHI Register (Offset = A8h) [Reset = 00000000h]

ADCPPB3TRIPHI is shown in Figure 12-90 and described in Table 12-91.

Return to the Summary Table.

ADC PPB3 Trip High Register

Figure 12-90 ADCPPB3TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 12-91 ADCPPB3TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITHIR/W0hADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[15:13] will be ignored

Reset type: SYSRSn

12.14.3.53 ADCPPB3TRIPLO Register (Offset = AAh) [Reset = 00000000h]

ADCPPB3TRIPLO is shown in Figure 12-91 and described in Table 12-92.

Return to the Summary Table.

ADC PPB3 Trip Low/Trigger Time Stamp Register

Figure 12-91 ADCPPB3TRIPLO Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 12-92 ADCPPB3TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LIMITLOR/W0hADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO[15:13] will be ignored in 12 bit mode

Reset type: SYSRSn

12.14.3.54 ADCINTCYCLE Register (Offset = C0h) [Reset = 00000000h]

ADCINTCYCLE is shown in Figure 12-92 and described in Table 12-93.

Return to the Summary Table.

ADC Early Interrupt Generation Cycle

Figure 12-92 ADCINTCYCLE Register
313029282726252423222120191817161514131211109876543210
RESERVEDDELAY
R-0hR/W-0h
Table 12-93 ADCINTCYCLE Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0DELAYR/W0hADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles, for the interrupt to be generated.

Reset type: SYSRSn

12.14.3.55 ADCINLTRIM1 Register (Offset = C2h) [Reset = X0000000h]

ADCINLTRIM1 is shown in Figure 12-93 and described in Table 12-94.

Return to the Summary Table.

ADC Linearity Trim 1 Register

Figure 12-93 ADCINLTRIM1 Register
313029282726252423222120191817161514131211109876543210
INLTRIM31TO0
R/W-Xh
Table 12-94 ADCINLTRIM1 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM31TO0R/WXhADC Linearity Trim Bits 31-0.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

12.14.3.56 ADCINLTRIM2 Register (Offset = C4h) [Reset = X0000000h]

ADCINLTRIM2 is shown in Figure 12-94 and described in Table 12-95.

Return to the Summary Table.

ADC Linearity Trim 2 Register

Figure 12-94 ADCINLTRIM2 Register
313029282726252423222120191817161514131211109876543210
INLTRIM63TO32
R/W-Xh
Table 12-95 ADCINLTRIM2 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM63TO32R/WXhADC Linearity Trim Bits 63-32.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

12.14.3.57 ADCREV2 Register (Offset = CEh) [Reset = 00000006h]

ADCREV2 is shown in Figure 12-95 and described in Table 12-96.

Return to the Summary Table.

ADC Wrapper Revision Register

Figure 12-95 ADCREV2 Register
31302928272625242322212019181716
WRAPPERREV
R-0h
1514131211109876543210
WRAPPERREVWRAPPERTYPE
R-0hR-6h
Table 12-96 ADCREV2 Register Field Descriptions
BitFieldTypeResetDescription
31-8WRAPPERREVR0hADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h.

Reset type: SYSRSn

7-0WRAPPERTYPER6hADC Wrapper Type. Always set to 6 for this ADC.

Reset type: SYSRSn

12.14.3.58 REP1CTL Register (Offset = E0h) [Reset = 00000000h]

REP1CTL is shown in Figure 12-96 and described in Table 12-97.

Return to the Summary Table.

ADC Trigger Repeater 1 Control Register

Figure 12-96 REP1CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
SWSYNCRESERVEDSYNCINSEL
R-0/W1S-0hR-0hR/W-0h
15141312111098
RESERVEDTRIGGER
R-0hR/W-0h
76543210
TRIGGEROVFRESERVEDRESERVEDRESERVEDMODULEBUSYRESERVEDRESERVEDRESERVED
R/W1C-0hR/W1C-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 12-97 REP1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23SWSYNCR-0/W1S0hTrigger repeater 1 software force sync. On a sync. event, all registers in Repeater 1 are reset to a ready and waiting state. Value of NSEL is preserved.

Note: SOCs associated with repeater 1 are not cleared.

Reset type: SYSRSn

22-19RESERVEDR0hReserved
18-16SYNCINSELR/W0hTrigger repeater 1 sync. input select. On a sync. event, all registers in Repeater 1 are reset to a ready and waiting state. Value of NSEL is preserved.

Note: SOCs associated with repeater 1 are not cleared.

0h = Disable Syncin to Repeater 1
1h - 1Fh = Hardware syncin sources

Reset type: SYSRSn

15-13RESERVEDR0hReserved
12-8TRIGGERR/W0hADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling.

00h REPTRIG0 - Software only
01h-1FH Hardware triggers

Reset type: SYSRSn

7TRIGGEROVFR/W1C0hADC Trigger Repeater 1 Oversampled Trigger Overflow.

Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 1 were still pending).

Writing a 1 will clear this flag.

Note: This flag won't be set when NSEL = 0
if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will remain set.

Reset type: SYSRSn

6RESERVEDR/W1C0hReserved
5RESERVEDR0hReserved
4RESERVEDR0hReserved
3MODULEBUSYR0hADC Trigger Repeater 1 Module Busy Indicator.

0 = Repeater 1 is idle and can accept a new repeated trigger
1 = Repeater 1 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1)

If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored.

Reset type: SYSRSn

2RESERVEDR0hReserved
1RESERVEDR0hReserved
0RESERVEDR/W0hReserved

12.14.3.59 REP1N Register (Offset = E2h) [Reset = 00000000h]

REP1N is shown in Figure 12-97 and described in Table 12-98.

Return to the Summary Table.

ADC Trigger Repeater 1 N Select Register

Figure 12-97 REP1N Register
31302928272625242322212019181716
RESERVEDNCOUNT
R-0hR-0h
1514131211109876543210
RESERVEDNSEL
R-0hR/W-0h
Table 12-98 REP1N Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16NCOUNTR0hADC trigger repeater 1 trigger count.

Indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP1CTL.TRIGOVF will be set to 1.

Reset type: SYSRSn

15-2RESERVEDR0hReserved
1-0NSELR/W0hADC Trigger Repeater 1 selection of number of triggers.

In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL, 2NSEL triggers will be generated.

0 = 1 trigger is generated (pass-through)
1 = 2 triggers are generated
2 = 4 triggers are generated
3 = 8 triggers are generated

In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP1CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed).

0 = all triggers are passed
1 = 1 out of 2 triggers are passed
2 = 1 out of 3 triggers are passed
...
127 = 1 out of 128 triggers are passed

Reset type: SYSRSn

12.14.3.60 REP1SPREAD Register (Offset = E6h) [Reset = 00000000h]

REP1SPREAD is shown in Figure 12-98 and described in Table 12-99.

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ADC Trigger Repeater 1 Spread Select Register

Figure 12-98 REP1SPREAD Register
313029282726252423222120191817161514131211109876543210
SPREADCOUNTSPREAD
R-0hR/W-0h
Table 12-99 REP1SPREAD Register Field Descriptions
BitFieldTypeResetDescription
31-16SPREADCOUNTR0hADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0.

The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP1CTL.BUSY = 0 (SOCs associated with trigger repeater 1 are no longer pending).

Reset type: SYSRSn

15-0SPREADR/W0hADC trigger repeater 1 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC.

If SPREAD is less than the time needed for all SOCs associated with repeater 1 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions.

If SPREAD is greater than the time needed for all SOCs associated with repeater 1 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart.

0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs
1 = time between repeated triggers is at least 1 SYSCLKs
2 = time between repeated triggers is at least 2 SYSCLKs
...
65535 = time between repeated triggers is at least 65535 SYSCLKs

Reset type: SYSRSn

12.14.3.61 REP1FRC Register (Offset = E8h) [Reset = 00000000h]

REP1FRC is shown in Figure 12-99 and described in Table 12-100.

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ADC Trigger Repeater 1 Software Force Register

Figure 12-99 REP1FRC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSWFRC
R-0hR-0/W1S-0h
Table 12-100 REP1FRC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SWFRCR-0/W1S0hWrite 1 to force a trigger to the Repeat Block 1 input regardless of the value of TRIGGER.

Always reads 0.

Reset type: SYSRSn

12.14.3.62 ADCPPB1LIMIT Register (Offset = 100h) [Reset = 00000000h]

ADCPPB1LIMIT is shown in Figure 12-100 and described in Table 12-101.

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ADC PPB1Conversion Count Limit Register

Figure 12-100 ADCPPB1LIMIT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDLIMIT
R-0hR/W-0h
Table 12-101 ADCPPB1LIMIT Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0LIMITR/W0hPost Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM.

0 = No - accumulation
1 = 2 conversions are accumulated
2 = 4 conversions are accumulated
3 = 8 conversions are accumulated

Reset type: SYSRSn

12.14.3.63 ADCPPBP1PCOUNT Register (Offset = 102h) [Reset = 00000000h]

ADCPPBP1PCOUNT is shown in Figure 12-101 and described in Table 12-102.

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ADC PPB1 Partial Conversion Count Register

Figure 12-101 ADCPPBP1PCOUNT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPCOUNT
R-0hR-0h
Table 12-102 ADCPPBP1PCOUNT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0PCOUNTR0hPost Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

12.14.3.64 ADCPPB1CONFIG2 Register (Offset = 104h) [Reset = 00000000h]

ADCPPB1CONFIG2 is shown in Figure 12-102 and described in Table 12-103.

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ADC PPB1 Sum Shift Register

Figure 12-102 ADCPPB1CONFIG2 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
COMPSELRESERVEDOSINTSELSWSYNCRESERVED
R/W-0hR-0hR/W-0hR-0/W1S-0hR-0h
76543210
RESERVEDSYNCINSELRESERVEDSHIFT
R-0hR/W-0hR-0hR/W-0h
Table 12-103 ADCPPB1CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15COMPSELR/W0hPost Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT, ADCPPB1PSUM, or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare.

0 = ADCPPB1RESULT is used for compare logic
1 = ADCPPB1SUM is used for compare logic


Note: when ADCPPB1PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB1LIMIT equals ADCPPB1COUNT) the ADCPPB1PSUM register will be cleared and the final sum will be loaded into ADCPPB1SUM. For this sample, the final sum, ADCPPB1SUM will be used for the comparison instead of ADCPPB1PSUM.

Reset type: SYSRSn

14-13RESERVEDR0hReserved
12OSINTSELR/W0hPost Processing Block 1 Interrupt Source Select.

OSINT1 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync event can trigger OSINT1 in addition to a PCOUNT = LIMIT event.

0 = OSINT1 will be generated from PCOUNT = LIMIT only
1 = OSTIN1 will be generated form PCOUNT = LIMIT or a sync. event.

Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.

Reset type: SYSRSn

11SWSYNCR-0/W1S0hPPB 1 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset.

Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.

Reset type: SYSRSn

10-7RESERVEDR0hReserved
6-4SYNCINSELR/W0hPPB 1 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
Refer to SOC spec for details

Reset type: SYSRSn

3RESERVEDR0hReserved
2-0SHIFTR/W0hPost Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM.

0 : no right shift
1 : SUM = PSUM >> 1
2 : SUM = PSUM >> 2
...
7 : SUM = PSUM >> 7

Reset type: SYSRSn

12.14.3.65 ADCPPB1PSUM Register (Offset = 106h) [Reset = 00000000h]

ADCPPB1PSUM is shown in Figure 12-103 and described in Table 12-104.

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ADC PPB1 Partial Sum Register

Figure 12-103 ADCPPB1PSUM Register
313029282726252423222120191817161514131211109876543210
SIGNPSUM
R-0hR-0h
Table 12-104 ADCPPB1PSUM Register Field Descriptions
BitFieldTypeResetDescription
31-16SIGNR0hSign Extended Bits. These bits reflect the same value as bit 15.

Reset type: SYSRSn

15-0PSUMR0hPost Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be available 2 SYSCLK cycles after the associated ADCRESULT. Subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles.

Reset type: SYSRSn