LMK04806
- Ultra-Low RMS Jitter Performance
- 111 fs RMS Jitter (12 kHz to 20 MHz)
- 123 fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator
Circuit - Holdover Mode when Input Clocks are Lost
- Automatic or Manual Triggering/Recovery
- Integrated Low-Noise Crystal Oscillator
- PLL2
- Normalized PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Integrated Low-Noise VCO
- 2 Redundant Input Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd) - 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs - Digital Delay: Fixed or Dynamically Adjustable
- 25 ps Step Analog Delay Control.
- 14 Differential Outputs. Up to 26 Single Ended.
- Up to 6 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 1536 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution - Industrial Temperature Range: –40 to 85°C
- 3.15-V to 3.45-V Operation
- 2 Dedicated Buffered/Divided OSCin Clocks
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK0480x family is the industrys highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 2014/12/24 |
User guide | TSW308x Evaluation Module (Rev. B) | 2016/05/18 | ||
EVM User's guide | TSW4806EVM User's Guide (Rev. A) | 2016/04/26 | ||
EVM User's guide | LMK0480x Evaluation Board Instructions (Rev. B) | 2014/08/04 | ||
Design guide | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 2013/09/03 | ||
Design guide | TSW308x Wideband Digital to RF Transmit Solution Design Guide | 2013/09/03 | ||
Application note | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 2013/07/12 | ||
User guide | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 2011/12/29 | ||
Design guide | Clock Conditioner Owner's Manual | 2006/11/10 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LMK04806BEVAL — 이중 계단식 PLL 및 통합 2.5GHz VCO가 장착된 클록 지터 클리너
The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum? architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using (...)
TSW1265EVM — 광대역 듀얼 리시버 레퍼런스 디자인 및 평가 플랫폼
The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)
TSW3084EVM — 광대역 전송 신호 체인 평가 보드 및 레퍼런스 디자인
The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)
TSW30H84EVM — 광대역 전송 신호 체인 평가 보드 및 레퍼런스 디자인
The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution (...)
SLAC532 — TSW4806 Installer GUI
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
지원되는 제품 및 하드웨어
제품
클록 생성기
RF PLL 및 신시사이저
클록 버퍼
클록 지터 클리너
하드웨어 개발
평가 보드
CLOCKDESIGNTOOL — Clock Design Tool Software
The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
지원되는 제품 및 하드웨어
제품
클록 생성기
RF PLL 및 신시사이저
클록 버퍼
클록 지터 클리너
CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
지원되는 제품 및 하드웨어
제품
RF PLL 및 신시사이저
클록 버퍼
클록 생성기
IQ 복조기
클록 지터 클리너
클록 네트워크 싱크로나이저
하드웨어 개발
평가 보드
소프트웨어
애플리케이션 소프트웨어 및 프레임워크
IDE, 구성, 컴파일러 또는 디버거
지원 소프트웨어
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TIDA-00076 — ACPR(인접 채널 전력비) 및 %EVM(오류 벡터 매그니튜드) 측정
TIDA-00072 — 광대역 디지털-RF 전송 솔루션
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
WQFN (NKD) | 64 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.