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AFE79XX-HSC-DESIGN — AFE79xx family high-speed transceiver design & support files
Find detailed product information on the AFE79xx product family (datasheets, EVM resources, software and firmware, reference designs, etc)
產品規格表
AFE7900
- Request full data sheet
- Quad RF sampling 12-GSPS transmit DACs
- Quad RF sampling 3-GSPS receive ADCs
- Dual RF sampling 3-GSPS feedback (auxilliary RX) ADCs
- Maximum RF signal bandwidth:
- 4TX or 2FB: 1200 MHz or 2TX: 2400 MHz
- RX): 1200 MHz (no FB), 600 MHz (with FB)
- RF frequency range:
- TX: 5MHz - 7.4GHz
- RX/FB: 5MHz - 7.4GHz
- Digital step attenuators (DSA):
- TX: 40 dB range, 0.125-dB steps
- RX or FB: 25 dB range, 0.5-dB steps
- Single or dual-band DUC or DDCs for TX and RX
- 16x NCOs per TX or RX and FB
- Optional Internal PLL or VCO for DAC or ADC clocks or external clock at DAC or ADC sample rate
- Sysref Alignment Detector
- SerDes data interface:
- JESD204B and JESD204C compatible
- 8 SerDes transceivers up to 29.5 Gbps
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
The AFE7900 is a high performance, wide bandwidth multi-channel transceiver, integrating four RF sampling transmitter chains, four RF sampling receiver chains and two RF sampling feedback chains (six RF sampling ADCs total). With operation up to 7.4 GHz, this device enables direct RF sampling in the L, S and C-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
The TX signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth for four TX or 2400 MHz for two TX. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
技術文件
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檢視所有 8 | 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | AFE7900 4T6R RF Sampling AFE with 12 GSPS DACs and 3 GSPS ADCs datasheet (Rev. B) | PDF | HTML | 2023年 6月 30日 |
| Application note | AFE79xx Bringup Using HDL Module Without Microcontroller | PDF | HTML | 2025年 8月 14日 | |
| Application note | AFE79XX as a Chirp Signal Generator | PDF | HTML | 2024年 7月 10日 | |
| Application note | Debugging AFE7950 for Run Time and Post Bring-Up Failure | PDF | HTML | 2024年 6月 28日 | |
| User guide | AFE79xx SPI Bringup Guide With Xilinx FPGAs (Rev. A) | PDF | HTML | 2024年 5月 5日 | |
| Application note | AFE79xx as Single Chip Wideband Repeater Solution (Rev. A) | PDF | HTML | 2023年 5月 30日 | |
| Application note | Determining Optimal Receive Buffer Delay in JESD204B and JESD204C Receivers | PDF | HTML | 2022年 7月 7日 | |
| Application note | How to Achieve Frequency Hopping with the AFE79xx | 2020年 7月 2日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
AFE7900EVM — 適用於四傳輸、六接收、5-MHz 至 7400-MHz、射頻取樣 AFE 的 AFE7900 評估模組
AFE7900 系列評估模組 (EVM) 是靈活的射頻取樣收發器平台，可配置為支援最多同時四個發射、四個接收與兩個回饋 (4T4R+2FB) 通道。此 EVM 設計可介接以下所示 TI 模式/擷取卡解決方案 (分開販售) 以及許多符合 FPGA FMC 標準的開發套件。
韌體
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支援產品和硬體
開發模組 (EVM) 的 GUI
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
支援產品和硬體
參考設計
TIDA-010230 — 適用雷達和 EW 應用的多通道射頻收發器、低雜訊時脈參考設計
在現代雷達和電子作戰 (EW) 系統中，有源電子掃描陣列 (AESA) 天線系統通常會搭配高速多通道 RF 收發器使用。這些系統需要能進行精確通道間偏斜調整的超低雜訊時脈，以獲得最佳系統性能，例如訊噪比 (SNR)、無雜散動態範圍 (SFDR)、IMD3 和有效位元數 (ENOB)。此參考設計展示了 LMX2820 和 LMK04832 架構的低雜訊 JESD204B 相容時脈，可為多個 AFE7950 提供最高 X 頻段的操作的並同步成 < 10 ps，此外可於 9-GSPS/3-GSPS DAC/ADC 時脈提高系統性能。
Design guide: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
| FCBGA (ALK) | 400 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。