DAC38J84
- Resolution: 16-Bit
- Maximum Sample Rate:
- DAC37J84: 1.6 GSPS
- DAC38J84: 2.5 GSPS
- Maximum Input Data Rate: 1.23GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC Synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x -16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Multi-Band Mode: Digital Summation of Independent
Complex Signals - 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Terminal-Compatible with Dual-Channel DAC37J82/
DAC38J82 Family - Power Dissipation: 1.8W at 2.5GSPS
- Package: 10x10mm, 144-Ball Flip-Chip BGA
The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
技術文件
設計與開發
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支援產品和硬體
產品
高速 DAC (>10 MSPS)
發射器
接收器
高速 ADC (≥10 MSPS)
射頻取樣收發器
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
發射器
接收器
高速 ADC (≥10 MSPS)
超音波 AFE
射頻取樣收發器
硬體開發
開發板
軟體
支援軟體
SLAC644 — DAC3XJ8XEVM Software
支援產品和硬體
產品
高速 DAC (>10 MSPS)
硬體開發
開發板
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
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TIDEP0081 — 使用 66AK2L06 JESD204B 連接 ADC32RF80 的寬頻接收器參考設計
TIDEP0060 — 使用 DSP+ARM SoC 的最佳化雷達系統參考設計
TIDEP0034 — 連接至寬頻 ADC 和 DAC 且具有 JESD204B 的 66AK2L06 DSP+ARM 處理器
TIDA-00996 — 同步多發送器參考設計:多個 DAC 實現時間對準的方法
TIDA-00409 — 最高達 4-GHz 的 1-GHz 頻寬雙通道發射器參考設計
TIDA-00335 — 高頻寬、高頻發射器參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
FCCSP (AAV) | 144 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。