The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. D) | PDF | HTML | 2019年 4月 17日 |
| Application note | Implementing the External DC Offset Correction Block in the ADS54J60 (Rev. A) | PDF | HTML | 2023年 6月 13日 | |
| User guide | HSDC Pro with Xilinx KCU105 | 2017年 3月 1日 | ||
| Technical article | How to minimize filter loss when you drive an ADC | PDF | HTML | 2016年 10月 20日 | |
| Analog Design Journal | JESD204B over optical fiber enables new architecture for phased-array radar | 2016年 1月 26日 | ||
| Technical article | RF sampling: interleaving builds faster ADCs | PDF | HTML | 2015年 10月 29日 | |
| Technical article | RF sampling: How over-sampling is cheating physics | PDF | HTML | 2015年 8月 21日 |
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADS54J60EVM 是一種評估模組 (EVM)，可用於評估德州儀器 (TI) 的 ADS54J60 和 LMK04828 時鐘抖動清除器。ADS54J60 是一款低功耗、16 位元、1-GSPS 類比轉數位轉換器 (ADC)，擁有具備 JESD204B 介面的緩衝類比輸入和輸出。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。LMK04828 為完整的 JESD204B 子類 1 計時解決方案，提供超低抖動和相位雜訊 ADC 取樣時鐘，以及系統參考時鐘和裝置取樣時鐘。
ADS54J60 和 LMK04828 是透過易於使用的軟體 GUI 進行控制，可針對各種用途快速配置。
(...)
The TSW54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60, LMH3401, LMH6401 and LMK04828 devices. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
Abaco FMC120 提供四個 16 位元類比數位轉換器 (ADC) 和四個 16 位元數位類比轉換器 (DAC)。本模組強調德州儀器兩項產品：ADS54J60 雙通道 16 位元 1-GSPS ADC（兩個）和 DAC39J84 四通道 16 位元 2.8-GSPS DAC（一個）位於子卡中，並配備使用 JEDEC JESD204B 資料轉換器數位介面的 FPGA 夾層介面卡 (FMC) 連接器。
FMC120 在機械和電氣方面均符合 FMC 標準 (ANSI/VITA 57.1)。該卡透過標準高針腳數 (HPC) 連接器連接到 FPGA 載卡。
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Analog Engineer's Calc Installer
General calculator tool for analog design support.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.