The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz.
In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain.
Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package.
The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates.
The device is specified over the industrial temperature range of –40°C to 85°C.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs datasheet (Rev. B) | PDF | HTML | 2016年 1月 13日 |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 | ||
| Application note | QFN Layout Guidelines | 2006年 7月 28日 |
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADS5560EVM 是能讓設計人員評估德州儀器 (TI) ADS5560 裝置 (具有高 SNR 性能的低功耗 16 位元 80MSPS 類比轉換器) 性能的電路板。ADC 具有可配置的並行 DDR LVDS 或 CMOS 輸出。EVM 提供了可在各種時鐘、輸入和電源條件下測試 ADS5562 的靈活環境。
ADS5560EVM 還包括開放式插槽和德州儀器 (TI) 的新款 10 輸出低抖動時鐘同步器和抖動消除器裝置 - CDCE72010，它可驅動 ADS5560 的時鐘輸入。我們為外部 VCXO 和晶體帶通濾波器提供了開放式插槽，允許對組合的高性能 ADC 與時鐘電路 (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Analog Engineer's Calc Installer
General calculator tool for analog design support.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.