SLWC120 — TSW14J57 ADC12DJ5200RF Reference Design Firmware
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
- ADC12DJ5200RF — 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的射頻取樣 12 位元 ADC
硬體開發
開發板
- TSW14J57EVM — 資料擷取/模式產生器:具有 16 個 JESD204B 通道 (1.6-15 Gbps) 的資料轉換器 EVM
The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
| FCCSP (ZEG) | 144 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Initial Release
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.